SPEC Seal of Reviewal OMPM2001 Result
Copyright © 1999-2007 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer p5 520 (1650 MHz, 2 CPU)
SPECompMpeak2001 = 5228     
SPECompMbase2001 = 5051     
SPEC license # HPG0005 Tested by: IBM Test site: Austin, TX Test date: Jun-2004 Hardware Avail: Aug-2004 Software Avail: Oct-2004
Benchmark Reference
Graph Scale
310.wupwise_m 6000 925    6486      925    6486      310.wupwise_m base result bar (6486)
310.wupwise_m peak result bar (6486)
312.swim_m 6000 1536     3907      1536     3907      312.swim_m base result bar (3907)
312.swim_m peak result bar (3907)
314.mgrid_m 7300 3490     2092      3490     2092      314.mgrid_m base result bar (2092)
314.mgrid_m peak result bar (2092)
316.applu_m 4000 793    5044      753    5314      316.applu_m base result bar (5044)
316.applu_m peak result bar (5314)
318.galgel_m 5100 405    12594       405    12594       318.galgel_m base result bar (12594)
318.galgel_m peak result bar (12594)
320.equake_m 2600 436    5964      393    6615      320.equake_m base result bar (5964)
320.equake_m peak result bar (6615)
324.apsi_m 3400 668    5089      668    5089      324.apsi_m base result bar (5089)
324.apsi_m peak result bar (5089)
326.gafort_m 8700 1611     5399      1612     5397      326.gafort_m base result bar (5399)
326.gafort_m peak result bar (5397)
328.fma3d_m 4600 1523     3020      1503     3061      328.fma3d_m base result bar (3020)
328.fma3d_m peak result bar (3061)
330.art_m 6400 551    11618       444    14408       330.art_m base result bar (11618)
330.art_m peak result bar (14408)
332.ammp_m 7000 2481     2821      2496     2804      332.ammp_m base result bar (2821)
332.ammp_m peak result bar (2804)
SPECompMbase2001 5051       
  SPECompMpeak2001 5228       

Hardware Vendor: IBM Corporation
Model Name: IBM eServer p5 520 (1650 MHz, 2 CPU)
CPU MHz: 1650
FPU: Integrated
CPU(s) enabled: 2 cores, 1 chip, 2 cores/chip (SMT on)
CPU(s) orderable: 2
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified (on chip)/chip
L3 Cache: 36MB unified (off chip)/DCM, 1 DCM/SUT
Other Cache: none
Memory: 8x4 GB
Disk Subsystem: 1x36GB SCSI, 15K RPM
Other Hardware:
OpenMP Threads: 4
Parallel: OpenMP
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 7.0 for AIX
XL Fortran Enterprise Edition V9.1 for AIX
Other Software: IBM Engineering and Scientific
Subroutine Library for AIX,
Version 4 Release 2
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information
Tested by IBM
 Portability Flags & Environment Variables
   Linker flag: -bmaxdata:0x80000000 used in all ca
   -qfixed used in: 310.wupwise_m, 312.swim_m, 314.mgrid_m, 316.applu_m, 324.apsi_m
   -qfixed=80 used in: 318.galgel_m
   -qsuffix=f=f90 used in: 318.galgel_m, 326.gafort_m, 328.fma3d_m
   Linker flag: -bmaxdata:0xD0000000 used in 330.art_m (for base and peak)
 Base Flags
   C: -q64 -O5 -qalign=natural -qipa=partition=large -qmaxmem=-1 -qsmp=omp
   FORTRAN:-O5 -qipa=partition=large -qmaxmem=-1 -qsmp=omp
 Base & Peak User Environment:
 Peak Flags
   -qsmp=omp used in all cases
   310.wupwise_m: basepeak=1
   312.swim_m:    -O5 -qtune=pwr5 -qarch=pwr5
   314.mgrid_m:   basepeak=1
   316.applu_m:   -O5 -qtune=pwr5 -qarch=pwr5
   318.galgel_m:  basepeak = 1
   320.equake_m:  -q64 -O5 -qalign=natural -qhot=arraypad -Q
   324.apsi_m:    basepeak=1
   326.gafort_m:  -O5 -qhot=arraypad -qipa=partition=large -qmaxmem=-1
   328.fma3d_m:   -O5 -qhot=arraypad -qipa=noobject
                  -qipa=partition=large -qmaxmem=-1
   330.art_m:     -qpdf1/pdf2
                  -q64 -O5 -blpdata -qalign=natural -qhot=arraypad -Q
   332.ammp_m:    -q64 -O5 -qalign=natural -qhot=arraypad -Q

 Alternate sources:
   Add critical region around update of linked list in parallel loop.
   Approved src.alt available as ompm-purdue1-20040324.tar.gz
   Used for 330.art_m, base and peak.
 Peak sources:
   SPEC OMPL2001 source for 32bit systems modified for SPEC OMPM2001 used
   with 312.swim_m, 316.applu_m, 320.equake_m, 326.gafort_m.

 SMT: Acronym for "Simultaneous Multi-Threading". A processor technology that allows
      the simultaneous execution of multiple thread contexts within a single processor
      core. (Enabled by default)
 DCM: Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
 SUT: Acronym for "System Under Test"
 C:          IBM XL C for AIX invoked as xlc_r
 Fortran 90: IBM XL Fortran for AIX invoked as xlf90_r
 ulimits set to unlimited.
 Large page mode and memory affinity were set as follows:
   vmo -r -o lgpg_regions=400 -o lgpg_size=16777216 -o memory_affinity=1
   reboot -q

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Copyright © 1999-2007 Standard Performance Evaluation Corporation

First published at SPEC.org on 06-Aug-2004

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