SPEC Seal of Reviewal OMPL2001 Result
Copyright © 1999-2002 Standard Performance Evaluation Corporation
Hewlett-Packard Company
HP Integrity Superdome 64-way (1500 MHz Itanium 2)
SPECompLpeak2001 = 271659       
SPECompLbase2001 = 257702       
SPEC license # HPG2116 Tested by: Hewlett-Packard Company Test site: Richardson, Texas Test date: Aug-2003 Hardware Avail: Oct-2003 Software Avail: Oct-2003
Benchmark Reference
Time
Base
Runtime
Base
Ratio
Peak
Runtime
Peak
Ratio
Graph Scale
311.wupwise_l 9200 399    369245        393    374257        311.wupwise_l base result bar (369245)
311.wupwise_l peak result bar (374257)
313.swim_l 12500 507    394202        507    394202        313.swim_l base result bar (394202)
313.swim_l peak result bar (394202)
315.mgrid_l 13500 1008     214301        1008     214301        315.mgrid_l base result bar (214301)
315.mgrid_l peak result bar (214301)
317.applu_l 13500 726    297382        646    334258        317.applu_l base result bar (297382)
317.applu_l peak result bar (334258)
321.equake_l 13000 2938     70791       2932     70931       321.equake_l base result bar (70791)
321.equake_l peak result bar (70931)
325.apsi_l 10500 675    248920        490    343044        325.apsi_l base result bar (248920)
325.apsi_l peak result bar (343044)
327.gafort_l 11000 714    246571        714    246571        327.gafort_l base result bar (246571)
327.gafort_l peak result bar (246571)
329.fma3d_l 23500 1345     279499        1345     279499        329.fma3d_l base result bar (279499)
329.fma3d_l peak result bar (279499)
331.art_l 25000 899    444961        880    454692        331.art_l base result bar (444961)
331.art_l peak result bar (454692)
SPECompLbase2001 257702         
  SPECompLpeak2001 271659         

Hardware
Hardware Vendor: Hewlett-Packard Company
Model Name: HP Integrity Superdome 64-way (1500 MHz Itanium 2)
CPU: Intel Itanium 2
CPU MHz: 1500
FPU: Integrated
CPU(s) enabled: 64
CPU(s) orderable: 6 to 64 by 2
Primary Cache: L1 Inst/Data: 16 KB, associativity = 4
Secondary Cache: L2 Unified: 256 KB, associativity = 8
L3 Cache: L3 Unified: 6144 KB, associativity = 24
Other Cache: None
Memory: 256GB (512 * 512MB DIMMs)
Disk Subsystem: root disk 1x36 SCSI
9x36GB Fibrechannel (striped)
Other Hardware: --
Software
OpenMP Threads: 64
Parallel: OpenMP
Operating System: HPUX11i-TCOE B.11.23
Compiler: HP C/ANSI C Compiler B.11.23
HP aC++ Compiler B.11.23
HP Fortran 90 Compiler B.11.23
HP LIBF90 PHSS_29620
HP F90 Compiler PHSS_29663
File System: vxfs
System State: Multi-user
Notes / Tuning Information
  User environment:
     MP_IDLE_THREADS_WAIT=-1
     OMP_FIRST_USE=0
 
  Base:
     F90  +Ofaster +DSitanium2 +Oopenmp   
          +Oinfo +DD64 -minshared  
     cc   +Ofaster +Oopenmp +DD64 +Oinfo +DSitanium2
          -minshared -AOe +Ofltacc=default
    submit = chatr -s +id disable +pd 64k +pi 64k $commandexe;  \
         _M_ARENA_OPTS=64:32 _M_SBA_OPTS=16348:150:256 \
            mpsched -T FILL $command 
  
  Peak:
    311.wupwise_l:  +Ofaster +O3 +DSitanium2 +Oopenmp 
      ONESTEP = true 
      +Oinfo +DD64 -minshared +cat -Wl,+pd64k -Wl,+pi64k
      submit = chatr -s +id disable $commandexe; 
          _M_ARENA_OPTS=64:32 mpsched -T FILL $command

    313.swim_l:  basepeak=true
 
    315.mgrid_l:  basepeak=true
 
    317.applu_l:  +Ofaster +DSitanium2  +Oopenmp +Oinfo 
      +DD64 -minshared
      ONESTEP=true
      submit = chatr -s +id enable $commandexe; 
          _M_ARENA_OPTS=64:32 mpsched -T FILL $command
 
    321.equake_l:  basepeak=true
 
    325.apsi_l: +Ofaster +DSitanium2 +Oopenmp +Oinfo +DD64 -minshared
        submit = chatr -s +id disable  +pd 256k +pi 256k $commandexe;  _
        M_ARENA_OPTS=64:32 mpsched -T FILL $command

    327.gafort_l: basepeak=true
 
    329.fma3d_l: basepeak=true
 
    331.art_l:  +Ofaster +Oopenmp +DD64 +Oinfo +DSitanium2
         -minshared -AOe +Ofltacc=default
      submit = chatr -s +id disable  +pd 256k +pi 256k  $commandexe; 
         _M_ARENA_OPTS=64:32  _M_SBA_OPTS=16348:150:256 mpsched -T FILL $command

 Alternate Sources:  
   ifdef version of art 
   from SPEC Web site  ompl2001-fabs-20030401.tar.gz
     used for Base and Peak 331.art_l
 
 
  Kernel Paramters (/stand/system):
     maxdsiz         0xc0000000
     maxdsiz_64bit   0x3ffbfffffff
     maxssiz         0x17f00000
     maxssiz_64bit   0x40000000
     maxtsiz         0x40000000
     maxtsiz_64bit   0x40000000
     vps_pagesize    4096
     vps_ceiling     16384
     dbc_min_pct     20
     dbc_max_pct     20
     swapmem_on      0
 
Notes:

  System was configured with 1/2 of memory interleaved and
    1/2 of memory local to each cell

  System configured as a single partition with 16 cells and 
    4 processors per cell

  Threads were assigned to cpus using the FILL strategy
    from the HP-UX mpsched utility

  Memory tuning is documented in man page malloc(3C)
    _M_ARENA_OPTS=64:32
      64 malloc arenas, 32 4k pages expansion
    _M_SBA_OPTS=16348:150:256
      16384 maxfast size, 150 small blocks, 256 grain size



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Copyright © 1999-2002 Standard Performance Evaluation Corporation

First published at SPEC.org on 17-Sep-2003

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