User environment:
     MP_IDLE_THREADS_WAIT=-1
     OMP_FIRST_USE=0
 
  Base:
     F90  +Ofaster +DSitanium2 +Oopenmp   
          +Oinfo +DD64 -minshared  
     cc   +Ofaster +Oopenmp +DD64 +Oinfo +DSitanium2
          -minshared -AOe +Ofltacc=default
    submit = chatr -s +id disable +pd 64k +pi 64k $commandexe;  \
         _M_ARENA_OPTS=64:32 _M_SBA_OPTS=16348:150:256 \
            mpsched -T FILL $command 
  
  Peak:
    311.wupwise_l:  +Ofaster +O3 +DSitanium2 +Oopenmp 
      ONESTEP = true 
      +Oinfo +DD64 -minshared +cat -Wl,+pd64k -Wl,+pi64k
      submit = chatr -s +id disable $commandexe; 
          _M_ARENA_OPTS=64:32 mpsched -T FILL $command

    313.swim_l:  basepeak=true
 
    315.mgrid_l:  basepeak=true
 
    317.applu_l:  +Ofaster +DSitanium2  +Oopenmp +Oinfo 
      +DD64 -minshared
      ONESTEP=true
      submit = chatr -s +id enable $commandexe; 
          _M_ARENA_OPTS=64:32 mpsched -T FILL $command
 
    321.equake_l:  basepeak=true
 
    325.apsi_l: +Ofaster +DSitanium2 +Oopenmp +Oinfo +DD64 -minshared
        submit = chatr -s +id disable  +pd 256k +pi 256k $commandexe;  _
        M_ARENA_OPTS=64:32 mpsched -T FILL $command

    327.gafort_l: basepeak=true
 
    329.fma3d_l: basepeak=true
 
    331.art_l:  +Ofaster +Oopenmp +DD64 +Oinfo +DSitanium2
         -minshared -AOe +Ofltacc=default
      submit = chatr -s +id disable  +pd 256k +pi 256k  $commandexe; 
         _M_ARENA_OPTS=64:32  _M_SBA_OPTS=16348:150:256 mpsched -T FILL $command

 Alternate Sources:  
   ifdef version of art 
   from SPEC Web site  ompl2001-fabs-20030401.tar.gz
     used for Base and Peak 331.art_l
 
 
  Kernel Paramters (/stand/system):
     maxdsiz         0xc0000000
     maxdsiz_64bit   0x3ffbfffffff
     maxssiz         0x17f00000
     maxssiz_64bit   0x40000000
     maxtsiz         0x40000000
     maxtsiz_64bit   0x40000000
     vps_pagesize    4096
     vps_ceiling     16384
     dbc_min_pct     20
     dbc_max_pct     20
     swapmem_on      0
 
Notes:

  System was configured with 1/2 of memory interleaved and
    1/2 of memory local to each cell

  System configured as a single partition with 16 cells and 
    4 processors per cell

  Threads were assigned to cpus using the FILL strategy
    from the HP-UX mpsched utility

  Memory tuning is documented in man page malloc(3C)
    _M_ARENA_OPTS=64:32
      64 malloc arenas, 32 4k pages expansion
    _M_SBA_OPTS=16348:150:256
      16384 maxfast size, 150 small blocks, 256 grain size