hpc2021 Flag Description

Test sponsored by Intel

Base Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Peak Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Base Portability Flags

605.lbm_s

613.soma_s

618.tealeaf_s

621.miniswp_s

634.hpgmgfv_s

Peak Portability Flags

605.lbm_s

613.soma_s

618.tealeaf_s

621.miniswp_s

634.hpgmgfv_s

Base Optimization Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Peak Optimization Flags

C benchmarks

605.lbm_s

613.soma_s

618.tealeaf_s

621.miniswp_s

634.hpgmgfv_s

C++ benchmarks

632.sph_exa_s

Fortran benchmarks

619.clvleaf_s

628.pot3d_s

635.weather_s

Base Other Flags

C benchmarks

Peak Other Flags

C benchmarks

Firmware / BIOS / Microcode Settings

HBM Memory Modes
HBM can be exposed to software using three different memory modes. These memory modes are selected through the BIOS menu when the system boots up. These modes are: HBM-only mode, Flat mode, Cache mode.
HBM-only Mode:
If the system does not have any DDR modules installed, it boots up in the HBM-only mode. In this mode, HBM appears to software as a single flat-memory address-space, no differently than how DDR is used on DDR-only-based systems. Existing software does not have to take any additional steps to use HBM memory in this mode.
Flat Mode:
When DDR modules are installed on a system, the user can select flat mode. In this mode, both DDR and HBM address spaces are visible to software. On a socket, each address space is exposed as a separate Non-uniform Memory Access (NUMA) node. By default, all allocations go to NUMA node 0, which is usually DDR. As a result, OS, and other services allocate memory from DDR, and therefore memory on HBM node is completely available for applications. This behavior is the primary advantage of flat mode as compared to the HBM-only mode, which uses HBM memory for non-application tasks. Exposing DDR and HBM as two separate NUMA nodes allows the use of standard Linux NUMA utilities and interfaces (for example, numactl and libnuma) to place an application in the desired address space.
Cache Mode:
On systems with both HBM and DDR, cache mode allows HBM to function as a memory-side cache, which caches the contents of DDR. In this mode, HBM is transparent to all software because the HBM cache is managed by hardware memory controllers. The entire DDR space is visible to software. Since the HBM cache is transparent to software, cache mode does not require any software modifications to take advantage of HBM. A symmetric population of DIMMs among the four memory controllers is required for cache mode. For best performance, all eight DDR channels should be populated. In cache mode, HBM is organized as a direct-mapped cache.

Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/hpc2021/flags/HBM.html,
http://www.spec.org/hpc2021/flags/Intel_compiler_flags.2024-12-11.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/hpc2021/flags/HBM.xml,
http://www.spec.org/hpc2021/flags/Intel_compiler_flags.2024-12-11.xml.

For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2021-2024 Standard Performance Evaluation Corporation
Tested with SPEC hpc2021 v1.1.8.
Report generated on 2024-12-20 14:52:08 by SPEC hpc2021 flags formatter v1.0.3 .