![[user]](https://www.spec.org/auto/hpc2021/images/user.png)
The Intel MPI C driver configured for use with the Intel oneAPI C compiler.
The Intel MPI C++ driver configured for use with the Intel oneAPI C++ compiler.
The Intel MPI Fortran driver configured for use with the Intel oneAPI Fortran compiler.
The Intel MPI C driver configured for use with the Intel oneAPI C compiler.
The Intel MPI C++ driver configured for use with the Intel oneAPI C++ compiler.
The Intel MPI Fortran driver configured for use with the Intel oneAPI Fortran compiler.
The Intel MPI Fortran driver configured for use with the Intel Classic Fortran compiler.
USE std C++ libs on Linker
Use C++ 14 language features.
USE std C++ libs on Linker
Use C++ 14 language features.
USE std C++ libs on Linker
Use C++ 14 language features.
USE std C++ libs on Linker
Use C++ 14 language features.
USE std C++ libs on Linker
Use C++ 14 language features.
USE std C++ libs on Linker
Use C++ 14 language features.
USE std C++ libs on Linker
Use C++ 14 language features.
USE std C++ libs on Linker
Use C++ 14 language features.
USE std C++ libs on Linker
Use C++ 14 language features.
USE std C++ libs on Linker
Use C++ 14 language features.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Enable -O3 -no-prec-div -fp-model fast=2 optimizations.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Determine if certain square root optimizations are enabled.
Allow aggressive, lossy floating-point optimizations.
Enable LTO (Link Time Optimization) in 'full' mode.
Turn on loop unroller.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Enable -O3 -no-prec-div -fp-model fast=2 optimizations.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Determine if certain square root optimizations are enabled.
Allow aggressive, lossy floating-point optimizations.
Enable LTO (Link Time Optimization) in 'full' mode.
Turn on loop unroller.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Enable -O3 -no-prec-div -fp-model fast=2 optimizations.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Determine if certain square root optimizations are enabled.
Allow aggressive, lossy floating-point optimizations.
Enable LTO (Link Time Optimization) in 'full' mode.
Turn on loop unroller.
Option standard-realloc-lhs (the default), tells the compiler that when the left-hand side of an assignment is an allocatable object, it should be reallocated to the shape of the right-hand side of the assignment before the assignment occurs. This is the current Fortran Standard definition. This feature may cause extra overhead at run time. This option has the same effect as option assume realloc_lhs.
If you specify nostandard-realloc-lhs, the compiler uses the old Fortran 2003 rules when interpreting assignment statements. The left-hand side is assumed to be allocated with the correct shape to hold the right-hand side. If it is not, incorrect behavior will occur. This option has the same effect as option assume norealloc_lhs.
The align toggle changes how data elements are aligned. Variables and arrays are analyzed and memory layout can be altered. Specifying array64byte will look for opportunities to transform and reailgn arrays to 64byte boundaries.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Enable -O3 -no-prec-div -fp-model fast=2 optimizations.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Determine if certain square root optimizations are enabled.
Allow aggressive, lossy floating-point optimizations.
Enable LTO (Link Time Optimization) in 'full' mode.
Turn on loop unroller.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Enable -O3 -no-prec-div -fp-model fast=2 optimizations.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Enable/disable(DEFAULT) use of ANSI aliasing rules in optimizations; user asserts that the program adheres to these rules.
Enable OpenMP compilation for hpc2021.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
-qopt-zmm-usage=
Specifies the level of zmm registers usage. You can specify one of
the following:
low - Tells the compiler that the compiled program is unlikely to
benefit from zmm registers usage. It specifies that the
compiler should avoid using zmm registers unless it can
prove the gain from their usage.
high - Tells the compiler to generate zmm code without restrictions
Determine if certain square root optimizations are enabled.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Enable -O3 -no-prec-div -fp-model fast=2 optimizations.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Determine if certain square root optimizations are enabled.
Allow aggressive, lossy floating-point optimizations.
Enable LTO (Link Time Optimization) in 'full' mode.
Turn on loop unroller.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Enable -O3 -no-prec-div -fp-model fast=2 optimizations.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Enable/disable(DEFAULT) use of ANSI aliasing rules in optimizations; user asserts that the program adheres to these rules.
Enable OpenMP compilation for hpc2021.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
-qopt-zmm-usage=
Specifies the level of zmm registers usage. You can specify one of
the following:
low - Tells the compiler that the compiled program is unlikely to
benefit from zmm registers usage. It specifies that the
compiler should avoid using zmm registers unless it can
prove the gain from their usage.
high - Tells the compiler to generate zmm code without restrictions
Determine if certain square root optimizations are enabled.
Option standard-realloc-lhs (the default), tells the compiler that when the left-hand side of an assignment is an allocatable object, it should be reallocated to the shape of the right-hand side of the assignment before the assignment occurs. This is the current Fortran Standard definition. This feature may cause extra overhead at run time. This option has the same effect as option assume realloc_lhs.
If you specify nostandard-realloc-lhs, the compiler uses the old Fortran 2003 rules when interpreting assignment statements. The left-hand side is assumed to be allocated with the correct shape to hold the right-hand side. If it is not, incorrect behavior will occur. This option has the same effect as option assume norealloc_lhs.
The align toggle changes how data elements are aligned. Variables and arrays are analyzed and memory layout can be altered. Specifying array64byte will look for opportunities to transform and reailgn arrays to 64byte boundaries.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Enable -O3 -no-prec-div -fp-model fast=2 optimizations.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Determine if certain square root optimizations are enabled.
Allow aggressive, lossy floating-point optimizations.
Enable LTO (Link Time Optimization) in 'full' mode.
Turn on loop unroller.
Specifies whether streaming stores are generated:
always - enables generation of streaming stores under the assumption that the application is memory bound
auto - compiler decides when streaming stores are used (DEFAULT)
never - disables generation of streaming stores
Option standard-realloc-lhs (the default), tells the compiler that when the left-hand side of an assignment is an allocatable object, it should be reallocated to the shape of the right-hand side of the assignment before the assignment occurs. This is the current Fortran Standard definition. This feature may cause extra overhead at run time. This option has the same effect as option assume realloc_lhs.
If you specify nostandard-realloc-lhs, the compiler uses the old Fortran 2003 rules when interpreting assignment statements. The left-hand side is assumed to be allocated with the correct shape to hold the right-hand side. If it is not, incorrect behavior will occur. This option has the same effect as option assume norealloc_lhs.
The align toggle changes how data elements are aligned. Variables and arrays are analyzed and memory layout can be altered. Specifying array64byte will look for opportunities to transform and reailgn arrays to 64byte boundaries.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Enable -O3 -no-prec-div -fp-model fast=2 optimizations.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Determine if certain square root optimizations are enabled.
Allow aggressive, lossy floating-point optimizations.
Enable LTO (Link Time Optimization) in 'full' mode.
Turn on loop unroller.
Option standard-realloc-lhs (the default), tells the compiler that when the left-hand side of an assignment is an allocatable object, it should be reallocated to the shape of the right-hand side of the assignment before the assignment occurs. This is the current Fortran Standard definition. This feature may cause extra overhead at run time. This option has the same effect as option assume realloc_lhs.
If you specify nostandard-realloc-lhs, the compiler uses the old Fortran 2003 rules when interpreting assignment statements. The left-hand side is assumed to be allocated with the correct shape to hold the right-hand side. If it is not, incorrect behavior will occur. This option has the same effect as option assume norealloc_lhs.
The align toggle changes how data elements are aligned. Variables and arrays are analyzed and memory layout can be altered. Specifying array64byte will look for opportunities to transform and reailgn arrays to 64byte boundaries.
Enable the specified warning.
Enable the specified warning.
Flag description origin markings:
|
Indicates that the flag description came from the user flags file. |
![[suite]](https://www.spec.org/auto/hpc2021/images/suite.png) |
Indicates that the flag description came from the suite-wide flags file. |
![[benchmark]](https://www.spec.org/auto/hpc2021/images/benchmark.png) |
Indicates that the flag description came from a per-benchmark flags file. |
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2021-2024 Standard Performance Evaluation Corporation
Tested with SPEC hpc2021 v1.1.8.
Report generated on 2024-01-10 17:35:03 by SPEC hpc2021 flags formatter v1.0.3 .