![[user]](https://www.spec.org/auto/hpc2021/images/user.png)
The Intel MPI C driver configured for use with the Intel C compiler.
The Intel MPI C++ driver configured for use with the Intel C++ compiler.
The Intel MPI Fortran driver configured for use with the Intel Fortran compiler.
The Intel MPI C driver configured for use with the Intel C compiler.
The Intel MPI C++ driver configured for use with the Intel C++ compiler.
The Intel MPI Fortran driver configured for use with the Intel Fortran compiler.
USE std C++ libs on Linker
USE std C++ libs on Linker
![[benchmark]](https://www.spec.org/auto/hpc2021/images/benchmark.png)
Disable use of reduction with variable array reduction variable (OpenMP 4.5, OpenACC 2.7) even if compiler reports support.
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
Disable use of reduction with variable array reduction variable (OpenMP 4.5, OpenACC 2.7) even if compiler reports support.
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
USE std C++ libs on Linker
Chooses generally optimal flags for the target platform.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
May generate Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® procesr. Optimizes for 4th, 5th and 6th generation Intel® Co processors and the Intel® Xeon® Processor E3 v3, E5 v3, E7 v3, E3 v4, E5 v4 and E7 v4 familie Available in compiler versions 13 and later.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enable/disable(DEFAULT) use of ANSI aliasing rules in optimizations; user asserts that the program adheres to these rules.
Chooses generally optimal flags for the target platform.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
May generate Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® procesr. Optimizes for 4th, 5th and 6th generation Intel® Co processors and the Intel® Xeon® Processor E3 v3, E5 v3, E7 v3, E3 v4, E5 v4 and E7 v4 familie Available in compiler versions 13 and later.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enable/disable(DEFAULT) use of ANSI aliasing rules in optimizations; user asserts that the program adheres to these rules.
Chooses generally optimal flags for the target platform.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
May generate Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® procesr. Optimizes for 4th, 5th and 6th generation Intel® Co processors and the Intel® Xeon® Processor E3 v3, E5 v3, E7 v3, E3 v4, E5 v4 and E7 v4 familie Available in compiler versions 13 and later.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Option standard-realloc-lhs (the default), tells the compiler that when the left-hand side of an assignment is an allocatable object, it should be reallocated to the shape of the right-hand side of the assignment before the assignment occurs. This is the current Fortran Standard definition. This feature may cause extra overhead at run time. This option has the same effect as option assume realloc_lhs.
If you specify nostandard-realloc-lhs, the compiler uses the old Fortran 2003 rules when interpreting assignment statements. The left-hand side is assumed to be allocated with the correct shape to hold the right-hand side. If it is not, incorrect behavior will occur. This option has the same effect as option assume norealloc_lhs.
The align toggle changes how data elements are aligned. Variables and arrays are analyzed and memory layout can be altered. Specifying array64byte will look for opportunities to transform and reailgn arrays to 64byte boundaries.
Chooses generally optimal flags for the target platform.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
May generate Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® procesr. Optimizes for 4th, 5th and 6th generation Intel® Co processors and the Intel® Xeon® Processor E3 v3, E5 v3, E7 v3, E3 v4, E5 v4 and E7 v4 familie Available in compiler versions 13 and later.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enable/disable(DEFAULT) use of ANSI aliasing rules in optimizations; user asserts that the program adheres to these rules.
Chooses generally optimal flags for the target platform.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
May generate Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® procesr. Optimizes for 4th, 5th and 6th generation Intel® Co processors and the Intel® Xeon® Processor E3 v3, E5 v3, E7 v3, E3 v4, E5 v4 and E7 v4 familie Available in compiler versions 13 and later.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enable/disable(DEFAULT) use of ANSI aliasing rules in optimizations; user asserts that the program adheres to these rules.
Chooses generally optimal flags for the target platform.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
May generate Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® procesr. Optimizes for 4th, 5th and 6th generation Intel® Co processors and the Intel® Xeon® Processor E3 v3, E5 v3, E7 v3, E3 v4, E5 v4 and E7 v4 familie Available in compiler versions 13 and later.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Option standard-realloc-lhs (the default), tells the compiler that when the left-hand side of an assignment is an allocatable object, it should be reallocated to the shape of the right-hand side of the assignment before the assignment occurs. This is the current Fortran Standard definition. This feature may cause extra overhead at run time. This option has the same effect as option assume realloc_lhs.
If you specify nostandard-realloc-lhs, the compiler uses the old Fortran 2003 rules when interpreting assignment statements. The left-hand side is assumed to be allocated with the correct shape to hold the right-hand side. If it is not, incorrect behavior will occur. This option has the same effect as option assume norealloc_lhs.
The align toggle changes how data elements are aligned. Variables and arrays are analyzed and memory layout can be altered. Specifying array64byte will look for opportunities to transform and reailgn arrays to 64byte boundaries.
![[suite]](https://www.spec.org/auto/hpc2021/images/suite.png)
Specifies a directory to search for include files. Use -I to add directories to the search path for include files.
Specifies a directory to search for include files. Use -I to add directories to the search path for include files.
Specifies a directory to search for include files. Use -I to add directories to the search path for include files.
Specifies a directory to search for include files. Use -I to add directories to the search path for include files.
Specifies a directory to search for include files. Use -I to add directories to the search path for include files.
Specifies a directory to search for include files. Use -I to add directories to the search path for include files.
Flag description origin markings:
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Indicates that the flag description came from the user flags file. |
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Indicates that the flag description came from the suite-wide flags file. |
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Indicates that the flag description came from a per-benchmark flags file. |
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2021-2023 Standard Performance Evaluation Corporation
Tested with SPEC hpc2021 v1.1.7.
Report generated on 2023-02-22 12:26:32 by SPEC hpc2021 flags formatter v1.0.3 .