SPEC CPU®2017 Integer Speed Result

Copyright 2017-2022 Standard Performance Evaluation Corporation

Cisco Systems

Cisco UCS X210c M6 (Intel Xeon Silver 4316,

SPECspeed®2017_int_base = 11.40

SPECspeed®2017_int_peak = Not Run

CPU2017 License: 9019 Test Date: Dec-2021
Test Sponsor: Cisco Systems Hardware Availability: Sep-2021
Tested by: Cisco Systems Software Availability: Sep-2021

Benchmark result graphs are available in the PDF report.

CPU Name: Intel Xeon Silver 4316
  Max MHz: 3400
  Nominal: 2300
Enabled: 40 cores, 2 chips
Orderable: 1,2 Chips
Cache L1: 32 KB I + 48 KB D on chip per core
  L2: 1.25 MB I+D on chip per core
  L3: 30 MB I+D on chip per chip
  Other: None
Memory: 1 TB (32 x 32 GB 2Rx4 PC4-3200AA-R,
running at 2666)
Storage: 1 x 240 GB M.2 SSD SATA
Other: None
OS: SUSE Linux Enterprise Server 15 SP2
Compiler: C/C++: Version 2021.4.0 of Intel oneAPI DPC++/C++
Compiler Build 20210924 for Linux;
Fortran: Version 2021.4.0 of Intel Fortran
Classic Build 20210910 for Linux;
Parallel: Yes
Firmware: Version 5.0.1d released Aug-2021
File System: btrfs
System State: Run level 3 (multi-user)
Base Pointers: 64-bit
Peak Pointers: Not Applicable
Other: jemalloc memory allocator V5.0.1
Power Management: BIOS and OS set to prefer performance at the cost
of additional power usage

Results Table

Benchmark Base Peak
Threads Seconds Ratio Seconds Ratio Seconds Ratio Threads Seconds Ratio Seconds Ratio Seconds Ratio
SPECspeed®2017_int_base 11.40
SPECspeed®2017_int_peak Not Run
Results appear in the order in which they were run. Bold underlined text indicates a median measurement.
600.perlbench_s 40 258 6.88 257 6.90 259 6.86
602.gcc_s 40 379 10.50 377 10.60 380 10.50
605.mcf_s 40 253 18.60 251 18.80 251 18.80
620.omnetpp_s 40 151 10.80 147 11.10 147 11.10
623.xalancbmk_s 40 111 12.80 110 12.90 110 12.90
625.x264_s 40 107 16.60 107 16.50 106 16.60
631.deepsjeng_s 40 249 5.75 249 5.75 249 5.75
641.leela_s 40 368 4.63 368 4.63 368 4.63
648.exchange2_s 40 156 18.90 157 18.80 156 18.80
657.xz_s 40 279 22.20 279 22.20 281 22.00

Submit Notes

 The numactl mechanism was used to bind copies to processors. The config file option 'submit'
 was used to generate numactl commands to bind each copy to a specific processor.
 For details, please see the config file.

Operating System Notes

 Stack size set to unlimited using "ulimit -s unlimited"

Environment Variables Notes

Environment variables set by runcpu before the start of the run:
KMP_AFFINITY = "granularity=fine,scatter"
MALLOC_CONF = "retain:true"

General Notes

 Binaries compiled on a system with 1x Intel Core i9-7940X CPU + 64GB RAM
 memory using openSUSE Leap 15.2
 Transparent Huge Pages enabled by default
 Prior to runcpu invocation
 Filesystem page cache synced and cleared with:
 sync; echo 3>       /proc/sys/vm/drop_caches
 runcpu command invoked through numactl i.e.:
 numactl --interleave=all runcpu <etc>
NA: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown)
is mitigated in the system as tested and documented.
Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1)
is mitigated in the system as tested and documented.
Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2)
is mitigated in the system as tested and documented.
 jemalloc, a general purpose malloc implementation
 built with the RedHat Enterprise 7.5, and the system compiler gcc 4.8.5
 sources available from jemalloc.net or https://github.com/jemalloc/jemalloc/releases

Platform Notes

BIOS Settings:
Adjacent Cache Line Prefetcher set to Disabled
DCU Streamer Prefetch set to Disabled
Sub NUMA Clustering set to Enabled
LLC Dead Line set to Disabled
Memory Refresh Rate set to 1x Refresh
ADDDC Sparing set to Disabled
Patrol Scrub set to Disabled
Intel Hyper-Threading Technology set to Disable
Processor C6 Report set to Enabled

 Sysinfo program /home/cpu2017/bin/sysinfo
 Rev: r6622 of 2021-04-07 982a61ec0915b55891ef0e16acafc64d
 running on perf-blade6 Fri Dec 10 08:51:06 2021

 SUT (System Under Test) info as seen by some common utilities.
 For more information on this section, see

 From /proc/cpuinfo
    model name : Intel(R) Xeon(R) Silver 4316 CPU @ 2.30GHz
       2  "physical id"s (chips)
       40 "processors"
    cores, siblings (Caution: counting these is hw and system dependent. The following
    excerpts from /proc/cpuinfo might not be reliable.  Use with caution.)
       cpu cores : 20
       siblings  : 20
       physical 0: cores 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
       physical 1: cores 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

 From lscpu from util-linux 2.33.1:
      Architecture:        x86_64
      CPU op-mode(s):      32-bit, 64-bit
      Byte Order:          Little Endian
      Address sizes:       46 bits physical, 57 bits virtual
      CPU(s):              40
      On-line CPU(s) list: 0-39
      Thread(s) per core:  1
      Core(s) per socket:  20
      Socket(s):           2
      NUMA node(s):        2
      Vendor ID:           GenuineIntel
      CPU family:          6
      Model:               106
      Model name:          Intel(R) Xeon(R) Silver 4316 CPU @ 2.30GHz
      Stepping:            6
      CPU MHz:             1374.206
      CPU max MHz:         3400.0000
      CPU min MHz:         800.0000
      BogoMIPS:            4600.00
      Virtualization:      VT-x
      L1d cache:           48K
      L1i cache:           32K
      L2 cache:            1280K
      L3 cache:            30720K
      NUMA node0 CPU(s):   0-19
      NUMA node1 CPU(s):   20-39
      Flags:               fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
      pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp
      lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid
      aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16
      xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave
      avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 invpcid_single ssbd
      mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad
      fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm rdt_a avx512f
      avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni
      avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total
      cqm_mbm_local wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp
      hwp_pkg_req avx512vbmi umip pku ospke avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni
      avx512_bitalg tme avx512_vpopcntdq la57 rdpid md_clear pconfig flush_l1d

 /proc/cpuinfo cache data
    cache size : 30720 KB

 From numactl --hardware
 WARNING: a numactl 'node' might or might not correspond to a physical chip.
   available: 2 nodes (0-1)
   node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
   node 0 size: 515651 MB
   node 0 free: 515070 MB
   node 1 cpus: 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
   node 1 size: 516087 MB
   node 1 free: 515630 MB
   node distances:
   node   0   1
     0:  10  20
     1:  20  10

 From /proc/meminfo
    MemTotal:       1056500564 kB
    HugePages_Total:       0
    Hugepagesize:       2048 kB

 /sys/devices/system/cpu/cpu*/cpufreq/scaling_governor has

 From /etc/*release* /etc/*version*
       PRETTY_NAME="SUSE Linux Enterprise Server 15 SP2"

 uname -a:
    Linux perf-blade6 5.3.18-22-default #1 SMP Wed Jun 3 12:16:43 UTC 2020 (720aeba)
    x86_64 x86_64 x86_64 GNU/Linux

 Kernel self-reported vulnerability status:

 CVE-2018-12207 (iTLB Multihit):                        Not affected
 CVE-2018-3620 (L1 Terminal Fault):                     Not affected
 Microarchitectural Data Sampling:                      Not affected
 CVE-2017-5754 (Meltdown):                              Not affected
 CVE-2018-3639 (Speculative Store Bypass):              Mitigation: Speculative Store
                                                        Bypass disabled via prctl and
 CVE-2017-5753 (Spectre variant 1):                     Mitigation: usercopy/swapgs
                                                        barriers and __user pointer
 CVE-2017-5715 (Spectre variant 2):                     Mitigation: Enhanced IBRS, IBPB:
                                                        conditional, RSB filling
 CVE-2020-0543 (Special Register Buffer Data Sampling): Not affected
 CVE-2019-11135 (TSX Asynchronous Abort):               Not affected

 run-level 3 Dec 10 08:50

 SPEC is set to: /home/cpu2017
    Filesystem     Type   Size  Used Avail Use% Mounted on
    /dev/sda2      btrfs  222G   41G  181G  19% /home

 From /sys/devices/virtual/dmi/id
     Vendor:         Cisco Systems Inc
     Product:        UCSX-210C-M6
     Serial:         FCH25057ANW

 Additional information from dmidecode 3.2 follows.  WARNING: Use caution when you
 interpret this section. The 'dmidecode' program reads system data which is "intended to
 allow hardware to be accurately determined", but the intent may not be met, as there are
 frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard.
     32x 0xCE00 M393A4K40DB3-CWE 32 GB 2 rank 3200, configured at 2666

    BIOS Vendor:       Cisco Systems, Inc.
    BIOS Version:      X210M6.5.0.1d.0.0816211754
    BIOS Date:         08/16/2021
    BIOS Revision:     5.22

 (End of data from sysinfo program)

Compiler Version Notes

C       | 600.perlbench_s(base) 602.gcc_s(base) 605.mcf_s(base)
        | 625.x264_s(base) 657.xz_s(base)
Intel(R) oneAPI DPC++/C++ Compiler for applications running on Intel(R) 64,
  Version 2021.4.0 Build 20210924
Copyright (C) 1985-2021 Intel Corporation. All rights reserved.

C++     | 620.omnetpp_s(base) 623.xalancbmk_s(base) 631.deepsjeng_s(base)
        | 641.leela_s(base)
Intel(R) oneAPI DPC++/C++ Compiler for applications running on Intel(R) 64,
  Version 2021.4.0 Build 20210924
Copyright (C) 1985-2021 Intel Corporation. All rights reserved.

Fortran | 648.exchange2_s(base)
Intel(R) Fortran Intel(R) 64 Compiler Classic for applications running on
  Intel(R) 64, Version 2021.4.0 Build 20210910_000000
Copyright (C) 1985-2021 Intel Corporation.  All rights reserved.

Base Compiler Invocation

C benchmarks:


C++ benchmarks:


Fortran benchmarks:


Base Portability Flags

600.perlbench_s:  -DSPEC_LP64   -DSPEC_LINUX_X64 
602.gcc_s:  -DSPEC_LP64 
605.mcf_s:  -DSPEC_LP64 
620.omnetpp_s:  -DSPEC_LP64 
623.xalancbmk_s:  -DSPEC_LP64   -DSPEC_LINUX 
625.x264_s:  -DSPEC_LP64 
631.deepsjeng_s:  -DSPEC_LP64 
641.leela_s:  -DSPEC_LP64 
648.exchange2_s:  -DSPEC_LP64 
657.xz_s:  -DSPEC_LP64 

Base Optimization Flags

C benchmarks:

 -DSPEC_OPENMP   -std=c11   -m64   -fiopenmp   -Wl,-z,muldefs   -xCORE-AVX512   -O3   -ffast-math   -flto   -mfpmath=sse   -funroll-loops   -qopt-mem-layout-trans=4   -mbranches-within-32B-boundaries   -L/home/cpu2017/je5.0.1-64   -ljemalloc 

C++ benchmarks:

 -DSPEC_OPENMP   -m64   -Wl,-z,muldefs   -xCORE-AVX512   -O3   -ffast-math   -flto   -mfpmath=sse   -funroll-loops   -qopt-mem-layout-trans=4   -mbranches-within-32B-boundaries   -L/home/intel/compiler/2021.4.0/linux/compiler/lib/intel64_lin/   -lqkmalloc 

Fortran benchmarks:

 -m64   -xCORE-AVX512   -O3   -ipo   -no-prec-div   -qopt-mem-layout-trans=4   -nostandard-realloc-lhs   -align array32byte   -auto   -mbranches-within-32B-boundaries 

The flags files that were used to format this result can be browsed at

You can also download the XML flags sources by saving the following links: