SPEC CPU®2017 Integer Speed Result

Copyright 2017-2020 Standard Performance Evaluation Corporation

Cisco Systems

Cisco UCS C240 M5 (Intel Xeon Silver 4215R,
3.20GHz)

SPECspeed®2017_int_base = 9.39

SPECspeed®2017_int_peak = 9.56

CPU2017 License: 9019 Test Date: Feb-2020
Test Sponsor: Cisco Systems Hardware Availability: Feb-2020
Tested by: Cisco Systems Software Availability: May-2019

Benchmark result graphs are available in the PDF report.

Hardware
CPU Name: Intel Xeon Silver 4215R
  Max MHz: 4000
  Nominal: 3200
Enabled: 16 cores, 2 chips
Orderable: 1,2 Chips
Cache L1: 32 KB I + 32 KB D on chip per core
  L2: 1 MB I+D on chip per core
  L3: 11 MB I+D on chip per chip
  Other: None
Memory: 768 GB (24 x 32 GB 2Rx4 PC4-2933V-R,
running at 2400)
Storage: 1 x 960 GB SSD SAS
Other: None
Software
OS: SUSE Linux Enterprise Server 15 (x86_64)
4.12.14-25.25-default
Compiler: C/C++: Version 19.0.4.227 of Intel C/C++
Compiler for Linux;
Fortran: Version 19.0.4.227 of Intel Fortran
Compiler for Linux
Parallel: Yes
Firmware: Version 4.0.4j released Aug-2019
File System: xfs
System State: Run level 5 (multi-user)
Base Pointers: 64-bit
Peak Pointers: 64-bit
Other: jemalloc memory allocator V5.0.1
Power Management: BIOS set to prefer performance at the cost of additional power usage

Results Table

Benchmark Base Peak
Threads Seconds Ratio Seconds Ratio Seconds Ratio Threads Seconds Ratio Seconds Ratio Seconds Ratio
SPECspeed®2017_int_base 9.39
SPECspeed®2017_int_peak 9.56
Results appear in the order in which they were run. Bold underlined text indicates a median measurement.
600.perlbench_s 16 275 6.45 273 6.51 274 6.47 16 237 7.48 237 7.50 237 7.50
602.gcc_s 16 458 8.70 453 8.80 457 8.72 16 446 8.93 447 8.91 445 8.94
605.mcf_s 16 386 12.20 384 12.30 386 12.20 16 382 12.40 383 12.30 383 12.30
620.omnetpp_s 16 313 5.21 310 5.26 311 5.24 16 315 5.17 314 5.19 316 5.15
623.xalancbmk_s 16 115 12.30 115 12.40 117 12.20 16 115 12.30 115 12.30 115 12.30
625.x264_s 16 132 13.40 131 13.40 131 13.40 16 131 13.40 131 13.40 131 13.40
631.deepsjeng_s 16 260 5.51 260 5.51 260 5.51 16 260 5.51 261 5.49 261 5.49
641.leela_s 16 349 4.89 349 4.89 349 4.89 16 349 4.89 349 4.89 349 4.89
648.exchange2_s 16 172 17.10 173 17.00 172 17.10 16 173 17.00 172 17.10 173 17.00
657.xz_s 16 319 19.40 318 19.40 319 19.40 16 314 19.70 313 19.70 314 19.70

Operating System Notes

 Stack size set to unlimited using "ulimit -s unlimited"

Environment Variables Notes

Environment variables set by runcpu before the start of the run:
KMP_AFFINITY = "granularity=fine,scatter"
LD_LIBRARY_PATH = "/home/cpu2017/lib/intel64:/home/cpu2017/je5.0.1-64"
OMP_STACKSIZE = "192M"

General Notes

 Binaries compiled on a system with 1x Intel Core i9-7900X CPU + 32GB RAM
 memory using Redhat Enterprise Linux 7.5
 Transparent Huge Pages enabled by default
 Prior to runcpu invocation
 Filesystem page cache synced and cleared with:
 sync; echo 3>       /proc/sys/vm/drop_caches
NA: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown)
is mitigated in the system as tested and documented.
Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1)
is mitigated in the system as tested and documented.
Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2)
is mitigated in the system as tested and documented.
 jemalloc, a general purpose malloc implementation
 built with the RedHat Enterprise 7.5, and the system compiler gcc 4.8.5
 sources available from jemalloc.net or https://github.com/jemalloc/jemalloc/releases

Platform Notes

BIOS Settings:
Intel HyperThreading Technology set to Disabled
CPU performance set to Enterprise
SNC set to Disabled
Patrol Scrub set to Disabled

 Sysinfo program /home/cpu2017/bin/sysinfo
 Rev: r6365 of 2019-08-21 295195f888a3d7edb1e6e46a485a0011
 running on linux-l7bx Mon Feb 24 17:36:36 2020

 SUT (System Under Test) info as seen by some common utilities.
 For more information on this section, see
    https://www.spec.org/cpu2017/Docs/config.html#sysinfo

 From /proc/cpuinfo
    model name : Intel(R) Xeon(R) Silver 4215R CPU @ 3.20GHz
       2  "physical id"s (chips)
       16 "processors"
    cores, siblings (Caution: counting these is hw and system dependent. The following
    excerpts from /proc/cpuinfo might not be reliable.  Use with caution.)
       cpu cores : 8
       siblings  : 8
       physical 0: cores 0 1 2 3 4 5 6 7
       physical 1: cores 0 1 2 3 4 5 6 7

 From lscpu:
      Architecture:        x86_64
      CPU op-mode(s):      32-bit, 64-bit
      Byte Order:          Little Endian
      CPU(s):              16
      On-line CPU(s) list: 0-15
      Thread(s) per core:  1
      Core(s) per socket:  8
      Socket(s):           2
      NUMA node(s):        2
      Vendor ID:           GenuineIntel
      CPU family:          6
      Model:               85
      Model name:          Intel(R) Xeon(R) Silver 4215R CPU @ 3.20GHz
      Stepping:            7
      CPU MHz:             3200.000
      CPU max MHz:         4000.0000
      CPU min MHz:         1000.0000
      BogoMIPS:            6400.00
      Virtualization:      VT-x
      L1d cache:           32K
      L1i cache:           32K
      L2 cache:            1024K
      L3 cache:            11264K
      NUMA node0 CPU(s):   0-7
      NUMA node1 CPU(s):   8-15
      Flags:               fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
      pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp
      lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid
      aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16
      xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave
      avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3
      invpcid_single intel_ppin ssbd mba ibrs ibpb stibp tpr_shadow vnmi flexpriority ept
      vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a
      avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl
      xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local
      dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req pku ospke avx512_vnni
      flush_l1d arch_capabilities

 /proc/cpuinfo cache data
    cache size : 11264 KB

 From numactl --hardware  WARNING: a numactl 'node' might or might not correspond to a
 physical chip.
   available: 2 nodes (0-1)
   node 0 cpus: 0 1 2 3 4 5 6 7
   node 0 size: 385574 MB
   node 0 free: 384652 MB
   node 1 cpus: 8 9 10 11 12 13 14 15
   node 1 size: 386830 MB
   node 1 free: 386257 MB
   node distances:
   node   0   1
     0:  10  21
     1:  21  10

 From /proc/meminfo
    MemTotal:       790942576 kB
    HugePages_Total:       0
    Hugepagesize:       2048 kB

 From /etc/*release* /etc/*version*
    os-release:
       NAME="SLES"
       VERSION="15"
       VERSION_ID="15"
       PRETTY_NAME="SUSE Linux Enterprise Server 15"
       ID="sles"
       ID_LIKE="suse"
       ANSI_COLOR="0;32"
       CPE_NAME="cpe:/o:suse:sles:15"

 uname -a:
    Linux linux-l7bx 4.12.14-25.25-default #1 SMP Thu Oct 25 16:07:27 UTC 2018 (d2d8b17)
    x86_64 x86_64 x86_64 GNU/Linux

 Kernel self-reported vulnerability status:

 CVE-2018-3620 (L1 Terminal Fault):        Not affected
 Microarchitectural Data Sampling:         No status reported
 CVE-2017-5754 (Meltdown):                 Not affected
 CVE-2018-3639 (Speculative Store Bypass): Mitigation: Speculative Store Bypass disabled
                                           via prctl and seccomp
 CVE-2017-5753 (Spectre variant 1):        Mitigation: __user pointer sanitization
 CVE-2017-5715 (Spectre variant 2):        Mitigation: Indirect Branch Restricted
                                           Speculation, IBPB, IBRS_FW

 run-level 5 Feb 24 17:33

 SPEC is set to: /home/cpu2017
    Filesystem     Type  Size  Used Avail Use% Mounted on
    /dev/sda3      xfs   324G   44G  280G  14% /home

 From /sys/devices/virtual/dmi/id
     BIOS:    Cisco Systems, Inc. C240M5.4.0.4j.0.0831191216 08/31/2019
     Vendor:  Cisco Systems Inc
     Product: UCSC-C240-M5L
     Serial:  WZP223909MB

 Additional information from dmidecode follows.  WARNING: Use caution when you interpret
 this section. The 'dmidecode' program reads system data which is "intended to allow
 hardware to be accurately determined", but the intent may not be met, as there are
 frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard.
   Memory:
     24x 0xCE00 M393A4K40CB2-CVF 32 GB 2 rank 2933, configured at 2400

 (End of data from sysinfo program)

Compiler Version Notes

==============================================================================
C       | 600.perlbench_s(base, peak) 602.gcc_s(base, peak) 605.mcf_s(base,
        | peak) 625.x264_s(base, peak) 657.xz_s(base, peak)
------------------------------------------------------------------------------
Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64,
  Version 19.0.4.227 Build 20190416
Copyright (C) 1985-2019 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

==============================================================================
C++     | 620.omnetpp_s(base, peak) 623.xalancbmk_s(base, peak)
        | 631.deepsjeng_s(base, peak) 641.leela_s(base, peak)
------------------------------------------------------------------------------
Intel(R) C++ Intel(R) 64 Compiler for applications running on Intel(R) 64,
  Version 19.0.4.227 Build 20190416
Copyright (C) 1985-2019 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

==============================================================================
Fortran | 648.exchange2_s(base, peak)
------------------------------------------------------------------------------
Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R)
  64, Version 19.0.4.227 Build 20190416
Copyright (C) 1985-2019 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

Base Compiler Invocation

C benchmarks:

 icc -m64 -std=c11 

C++ benchmarks:

 icpc -m64 

Fortran benchmarks:

 ifort -m64 

Base Portability Flags

600.perlbench_s:  -DSPEC_LP64   -DSPEC_LINUX_X64 
602.gcc_s:  -DSPEC_LP64 
605.mcf_s:  -DSPEC_LP64 
620.omnetpp_s:  -DSPEC_LP64 
623.xalancbmk_s:  -DSPEC_LP64   -DSPEC_LINUX 
625.x264_s:  -DSPEC_LP64 
631.deepsjeng_s:  -DSPEC_LP64 
641.leela_s:  -DSPEC_LP64 
648.exchange2_s:  -DSPEC_LP64 
657.xz_s:  -DSPEC_LP64 

Base Optimization Flags

C benchmarks:

 -Wl,-z,muldefs   -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-mem-layout-trans=4   -qopenmp   -DSPEC_OPENMP   -L/usr/local/je5.0.1-64/lib   -ljemalloc 

C++ benchmarks:

 -Wl,-z,muldefs   -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-mem-layout-trans=4   -L/usr/local/IntelCompiler19/compilers_and_libraries_2019.4.227/linux/compiler/lib/intel64   -lqkmalloc 

Fortran benchmarks:

 -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-mem-layout-trans=4   -nostandard-realloc-lhs 

Peak Compiler Invocation

C benchmarks:

 icc -m64 -std=c11 

C++ benchmarks:

 icpc -m64 

Fortran benchmarks:

 ifort -m64 

Peak Portability Flags

Same as Base Portability Flags

Peak Optimization Flags

C benchmarks:

600.perlbench_s:  -Wl,-z,muldefs   -prof-gen(pass 1)   -prof-use(pass 2)   -O2   -xCORE-AVX512   -qopt-mem-layout-trans=4   -ipo   -O3   -no-prec-div   -DSPEC_SUPPRESS_OPENMP   -qopenmp   -DSPEC_OPENMP   -fno-strict-overflow   -L/usr/local/je5.0.1-64/lib   -ljemalloc 
602.gcc_s:  -Wl,-z,muldefs   -prof-gen(pass 1)   -prof-use(pass 2)   -O2   -xCORE-AVX512   -qopt-mem-layout-trans=4   -ipo   -O3   -no-prec-div   -DSPEC_SUPPRESS_OPENMP   -L/usr/local/je5.0.1-64/lib   -ljemalloc 
605.mcf_s:  -Wl,-z,muldefs   -prof-gen(pass 1)   -prof-use(pass 2)   -ipo   -xCORE-AVX512   -O3   -no-prec-div   -qopt-mem-layout-trans=4   -DSPEC_SUPPRESS_OPENMP   -qopenmp   -DSPEC_OPENMP   -L/usr/local/je5.0.1-64/lib   -ljemalloc 
625.x264_s:  -Wl,-z,muldefs   -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-mem-layout-trans=4   -qopenmp   -DSPEC_OPENMP   -L/usr/local/je5.0.1-64/lib   -ljemalloc 
657.xz_s:  -Wl,-z,muldefs   -prof-gen(pass 1)   -prof-use(pass 2)   -O2   -xCORE-AVX512   -qopt-mem-layout-trans=4   -ipo   -O3   -no-prec-div   -DSPEC_SUPPRESS_OPENMP   -qopenmp   -DSPEC_OPENMP   -L/usr/local/je5.0.1-64/lib   -ljemalloc 

C++ benchmarks:

620.omnetpp_s:  -Wl,-z,muldefs   -prof-gen(pass 1)   -prof-use(pass 2)   -ipo   -xCORE-AVX512   -O3   -no-prec-div   -qopt-mem-layout-trans=4   -DSPEC_SUPPRESS_OPENMP   -L/usr/local/IntelCompiler19/compilers_and_libraries_2019.4.227/linux/compiler/lib/intel64   -lqkmalloc 
623.xalancbmk_s:  -Wl,-z,muldefs   -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-mem-layout-trans=4   -L/usr/local/IntelCompiler19/compilers_and_libraries_2019.4.227/linux/compiler/lib/intel64   -lqkmalloc 
631.deepsjeng_s:  Same as 623.xalancbmk_s 
641.leela_s:  Same as 623.xalancbmk_s 

Fortran benchmarks:

 -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-mem-layout-trans=4   -nostandard-realloc-lhs 

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/Intel-ic19.0u1-official-linux64.2019-07-09.html,
http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revJ.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/Intel-ic19.0u1-official-linux64.2019-07-09.xml,
http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revJ.xml.