SPEC CPU(R)2017 Floating Point Speed Result Cisco Systems Cisco UCS C480 M5 (Intel Xeon Gold 5215, 2.50GHz) CPU2017 License: 9019 Test date: Oct-2019 Test sponsor: Cisco Systems Hardware availability: Apr-2019 Tested by: Cisco Systems Software availability: May-2019 Base Base Base Peak Peak Peak Benchmarks Threads Run Time Ratio Threads Run Time Ratio --------------- ------- --------- --------- ------- --------- --------- 603.bwaves_s 40 87.6 673 * 603.bwaves_s 40 87.0 678 S 603.bwaves_s 40 88.2 669 S 607.cactuBSSN_s 40 126 132 * 607.cactuBSSN_s 40 127 132 S 607.cactuBSSN_s 40 125 133 S 619.lbm_s 40 39.0 134 * 619.lbm_s 40 39.5 133 S 619.lbm_s 40 38.3 137 S 621.wrf_s 40 134 98.6 S 621.wrf_s 40 133 99.6 S 621.wrf_s 40 133 99.3 * 627.cam4_s 40 102 86.8 * 627.cam4_s 40 102 86.6 S 627.cam4_s 40 102 86.8 S 628.pop2_s 40 208 57.0 * 628.pop2_s 40 207 57.3 S 628.pop2_s 40 211 56.2 S 638.imagick_s 40 123 117 S 638.imagick_s 40 123 118 S 638.imagick_s 40 123 118 * 644.nab_s 40 80.1 218 S 644.nab_s 40 80.2 218 S 644.nab_s 40 80.2 218 * 649.fotonik3d_s 40 91.5 99.6 S 649.fotonik3d_s 40 90.5 101 * 649.fotonik3d_s 40 89.4 102 S 654.roms_s 40 154 102 * 654.roms_s 40 146 108 S 654.roms_s 40 158 99.8 S ================================================================================= 603.bwaves_s 40 87.6 673 * 607.cactuBSSN_s 40 126 132 * 619.lbm_s 40 39.0 134 * 621.wrf_s 40 133 99.3 * 627.cam4_s 40 102 86.8 * 628.pop2_s 40 208 57.0 * 638.imagick_s 40 123 118 * 644.nab_s 40 80.2 218 * 649.fotonik3d_s 40 90.5 101 * 654.roms_s 40 154 102 * SPECspeed(R)2017_fp_base 132 SPECspeed(R)2017_fp_peak Not Run HARDWARE -------- CPU Name: Intel Xeon Gold 5215 Max MHz: 3400 Nominal: 2500 Enabled: 40 cores, 4 chips Orderable: 2,4 Chips Cache L1: 32 KB I + 32 KB D on chip per core L2: 1 MB I+D on chip per core L3: 13.75 MB I+D on chip per chip Other: None Memory: 1536 GB (48 x 32 GB 2Rx4 PC4-2933V-R, running at 2666) Storage: 1 x 600 GB 15K RPM SAS HDD Other: None SOFTWARE -------- OS: SUSE Linux Enterprise Server 15 (x86_64) 4.12.14-25.28-default Compiler: C/C++: Version 19.0.4.227 of Intel C/C++ Compiler for Linux; Fortran: Version 19.0.4.227 of Intel Fortran Compiler for Linux Parallel: Yes Firmware: Version 4.0.4g released Jul-2019 File System: xfs System State: Run level 3 (multi-user) Base Pointers: 64-bit Peak Pointers: Not Applicable Other: None Power Management: default Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" Environment Variables Notes --------------------------- Environment variables set by runcpu before the start of the run: KMP_AFFINITY = "granularity=fine,compact" LD_LIBRARY_PATH = "/home/cpu2017/lib/intel64" OMP_STACKSIZE = "192M" General Notes ------------- Binaries compiled on a system with 1x Intel Core i9-7900X CPU + 32GB RAM memory using Redhat Enterprise Linux 7.5 Transparent Huge Pages enabled by default Prior to runcpu invocation Filesystem page cache synced and cleared with: sync; echo 3> /proc/sys/vm/drop_caches NA: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2) is mitigated in the system as tested and documented. Platform Notes -------------- BIOS Settings: Intel HyperThreading Technology set to Disabled CPU performance set to Enterprise Power Performance Tuning set to OS Controls SNC set to Disabled Patrol Scrub set to Disabled Sysinfo program /home/cpu2017/bin/sysinfo Rev: r6365 of 2019-08-21 295195f888a3d7edb1e6e46a485a0011 running on linux-75co Wed Oct 23 09:52:35 2019 SUT (System Under Test) info as seen by some common utilities. For more information on this section, see https://www.spec.org/cpu2017/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Gold 5215 CPU @ 2.50GHz 4 "physical id"s (chips) 40 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 10 siblings : 10 physical 0: cores 0 1 2 3 4 8 9 10 11 12 physical 1: cores 0 1 2 3 4 8 9 10 11 12 physical 2: cores 0 1 2 3 4 8 9 10 11 12 physical 3: cores 0 1 2 3 4 8 9 10 11 12 From lscpu: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 40 On-line CPU(s) list: 0-39 Thread(s) per core: 1 Core(s) per socket: 10 Socket(s): 4 NUMA node(s): 4 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Gold 5215 CPU @ 2.50GHz Stepping: 6 CPU MHz: 2500.000 CPU max MHz: 3400.0000 CPU min MHz: 1000.0000 BogoMIPS: 5000.00 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 14080K NUMA node0 CPU(s): 0-9 NUMA node1 CPU(s): 10-19 NUMA node2 CPU(s): 20-29 NUMA node3 CPU(s): 30-39 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single intel_ppin ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req pku ospke avx512_vnni flush_l1d arch_capabilities /proc/cpuinfo cache data cache size : 14080 KB From numactl --hardware WARNING: a numactl 'node' might or might not correspond to a physical chip. available: 4 nodes (0-3) node 0 cpus: 0 1 2 3 4 5 6 7 8 9 node 0 size: 385609 MB node 0 free: 385313 MB node 1 cpus: 10 11 12 13 14 15 16 17 18 19 node 1 size: 387069 MB node 1 free: 386690 MB node 2 cpus: 20 21 22 23 24 25 26 27 28 29 node 2 size: 387069 MB node 2 free: 386805 MB node 3 cpus: 30 31 32 33 34 35 36 37 38 39 node 3 size: 387068 MB node 3 free: 382973 MB node distances: node 0 1 2 3 0: 10 21 21 31 1: 21 10 31 21 2: 21 31 10 21 3: 31 21 21 10 From /proc/meminfo MemTotal: 1583941372 kB HugePages_Total: 0 Hugepagesize: 2048 kB From /etc/*release* /etc/*version* os-release: NAME="SLES" VERSION="15" VERSION_ID="15" PRETTY_NAME="SUSE Linux Enterprise Server 15" ID="sles" ID_LIKE="suse" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:15" uname -a: Linux linux-75co 4.12.14-25.28-default #1 SMP Wed Jan 16 20:00:47 UTC 2019 (dd6077c) x86_64 x86_64 x86_64 GNU/Linux Kernel self-reported vulnerability status: CVE-2018-3620 (L1 Terminal Fault): Not affected Microarchitectural Data Sampling: No status reported CVE-2017-5754 (Meltdown): Not affected CVE-2018-3639 (Speculative Store Bypass): Mitigation: Speculative Store Bypass disabled via prctl and seccomp CVE-2017-5753 (Spectre variant 1): Mitigation: __user pointer sanitization CVE-2017-5715 (Spectre variant 2): Mitigation: Enhanced IBRS, IBPB: conditional, RSB filling run-level 3 Oct 23 07:08 SPEC is set to: /home/cpu2017 Filesystem Type Size Used Avail Use% Mounted on /dev/sda3 xfs 177G 72G 106G 41% /home From /sys/devices/virtual/dmi/id BIOS: Cisco Systems, Inc. C480M5.4.0.4g.0.0712190013 07/12/2019 Vendor: Cisco Systems Inc Product: UCSC-C480-M5 Serial: FCH2223W00A Additional information from dmidecode follows. WARNING: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. Memory: 48x 0xCE00 M393A4K40CB2-CVF 32 GB 2 rank 2933, configured at 2666 (End of data from sysinfo program) Compiler Version Notes ---------------------- ============================================================================== C | 619.lbm_s(base) 638.imagick_s(base) 644.nab_s(base) ------------------------------------------------------------------------------ Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.4.227 Build 20190416 Copyright (C) 1985-2019 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C++, C, Fortran | 607.cactuBSSN_s(base) ------------------------------------------------------------------------------ Intel(R) C++ Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.4.227 Build 20190416 Copyright (C) 1985-2019 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.4.227 Build 20190416 Copyright (C) 1985-2019 Intel Corporation. All rights reserved. Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.4.227 Build 20190416 Copyright (C) 1985-2019 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran | 603.bwaves_s(base) 649.fotonik3d_s(base) 654.roms_s(base) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.4.227 Build 20190416 Copyright (C) 1985-2019 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran, C | 621.wrf_s(base) 627.cam4_s(base) 628.pop2_s(base) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.4.227 Build 20190416 Copyright (C) 1985-2019 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.4.227 Build 20190416 Copyright (C) 1985-2019 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ Base Compiler Invocation ------------------------ C benchmarks: icc -m64 -std=c11 Fortran benchmarks: ifort -m64 Benchmarks using both Fortran and C: ifort -m64 icc -m64 -std=c11 Benchmarks using Fortran, C, and C++: icpc -m64 icc -m64 -std=c11 ifort -m64 Base Portability Flags ---------------------- 603.bwaves_s: -DSPEC_LP64 607.cactuBSSN_s: -DSPEC_LP64 619.lbm_s: -DSPEC_LP64 621.wrf_s: -DSPEC_LP64 -DSPEC_CASE_FLAG -convert big_endian 627.cam4_s: -DSPEC_LP64 -DSPEC_CASE_FLAG 628.pop2_s: -DSPEC_LP64 -DSPEC_CASE_FLAG -convert big_endian -assume byterecl 638.imagick_s: -DSPEC_LP64 644.nab_s: -DSPEC_LP64 649.fotonik3d_s: -DSPEC_LP64 654.roms_s: -DSPEC_LP64 Base Optimization Flags ----------------------- C benchmarks: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -DSPEC_OPENMP Fortran benchmarks: -DSPEC_OPENMP -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -nostandard-realloc-lhs Benchmarks using both Fortran and C: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -DSPEC_OPENMP -nostandard-realloc-lhs Benchmarks using Fortran, C, and C++: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -DSPEC_OPENMP -nostandard-realloc-lhs The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2017/flags/Intel-ic19.0u1-official-linux64.2019-07-09.html http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revJ.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2017/flags/Intel-ic19.0u1-official-linux64.2019-07-09.xml http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revJ.xml SPEC CPU and SPECspeed are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ---------------------------------------------------------------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact info@spec.org. Copyright 2017-2020 Standard Performance Evaluation Corporation Tested with SPEC CPU(R)2017 v1.1.0 on 2019-10-23 12:52:34-0400. Report generated on 2020-07-23 15:39:28 by CPU2017 text formatter v6255. Originally published on 2019-11-25.