SPEC CPU(R)2017 Integer Rate Result Cisco Systems Cisco UCS B200 M5 (Intel Xeon Gold 6238, 2.10GHz) CPU2017 License: 9019 Test date: Aug-2019 Test sponsor: Cisco Systems Hardware availability: Apr-2019 Tested by: Cisco Systems Software availability: May-2019 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate --------------- ------- --------- --------- ------- --------- --------- 500.perlbench_r 88 751 187 * 500.perlbench_r 88 750 187 S 500.perlbench_r 88 752 186 S 502.gcc_r 88 635 196 S 502.gcc_r 88 640 195 S 502.gcc_r 88 637 196 * 505.mcf_r 88 458 310 * 505.mcf_r 88 456 312 S 505.mcf_r 88 460 309 S 520.omnetpp_r 88 708 163 S 520.omnetpp_r 88 708 163 * 520.omnetpp_r 88 709 163 S 523.xalancbmk_r 88 358 259 * 523.xalancbmk_r 88 357 260 S 523.xalancbmk_r 88 359 259 S 525.x264_r 88 312 494 S 525.x264_r 88 311 495 * 525.x264_r 88 311 496 S 531.deepsjeng_r 88 508 199 S 531.deepsjeng_r 88 511 198 S 531.deepsjeng_r 88 509 198 * 541.leela_r 88 768 190 S 541.leela_r 88 760 192 S 541.leela_r 88 765 190 * 548.exchange2_r 88 461 500 * 548.exchange2_r 88 462 499 S 548.exchange2_r 88 461 500 S 557.xz_r 88 579 164 S 557.xz_r 88 579 164 * 557.xz_r 88 579 164 S ================================================================================= 500.perlbench_r 88 751 187 * 502.gcc_r 88 637 196 * 505.mcf_r 88 458 310 * 520.omnetpp_r 88 708 163 * 523.xalancbmk_r 88 358 259 * 525.x264_r 88 311 495 * 531.deepsjeng_r 88 509 198 * 541.leela_r 88 765 190 * 548.exchange2_r 88 461 500 * 557.xz_r 88 579 164 * SPECrate(R)2017_int_base 244 SPECrate(R)2017_int_peak Not Run HARDWARE -------- CPU Name: Intel Xeon Gold 6238 Max MHz: 3700 Nominal: 2100 Enabled: 44 cores, 2 chips, 2 threads/core Orderable: 1,2 Chips Cache L1: 32 KB I + 32 KB D on chip per core L2: 1 MB I+D on chip per core L3: 30.25 MB I+D on chip per chip Other: None Memory: 768 GB (24 x 32 GB 2Rx4 PC4-2933V-R) Storage: 1 x 240 GB M.2 SATA SSD Other: None SOFTWARE -------- OS: SUSE Linux Enterprise Server 15 (x86_64) 4.12.14-23-default Compiler: C/C++: Version 19.0.4.227 of Intel C/C++ Compiler for Linux; Fortran: Version 19.0.4.227 of Intel Fortran Compiler for Linux Parallel: No Firmware: Version 4.0.4b released Apr-2019 File System: xfs System State: Run level 3 (multi-user) Base Pointers: 64-bit Peak Pointers: Not Applicable Other: None Power Management: -- Submit Notes ------------ The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" General Notes ------------- Environment variables set by runcpu before the start of the run: LD_LIBRARY_PATH = "/home/cpu2017/lib/intel64:/home/cpu2017/lib/ia32:/home/cpu2017/je5.0.1-32" Binaries compiled on a system with 1x Intel Core i9-7900X CPU + 32GB RAM memory using Redhat Enterprise Linux 7.5 Transparent Huge Pages enabled by default Prior to runcpu invocation Filesystem page cache synced and cleared with: sync; echo 3> /proc/sys/vm/drop_caches runcpu command invoked through numactl i.e.: numactl --interleave=all runcpu NA: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2) is mitigated in the system as tested and documented. Platform Notes -------------- BIOS Settings: Intel HyperThreading Technology set to Enabled CPU performance set to Enterprise Power Performance Tuning set to OS Controls SNC set to Enabled IMC Interleaving set to 1-way Interleave Patrol Scrub set to Disabled Sysinfo program /home/cpu2017/bin/sysinfo Rev: r5797 of 2017-06-14 96c45e4568ad54c135fd618bcc091c0f running on linux-aixk Mon Aug 19 09:11:16 2019 SUT (System Under Test) info as seen by some common utilities. For more information on this section, see https://www.spec.org/cpu2017/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Gold 6238 CPU @ 2.10GHz 2 "physical id"s (chips) 88 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 22 siblings : 44 physical 0: cores 0 1 2 3 4 5 8 9 10 11 12 16 17 18 19 20 21 24 25 26 27 28 physical 1: cores 0 1 2 3 4 5 8 9 10 11 12 16 17 18 19 20 21 24 25 26 27 28 From lscpu: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 88 On-line CPU(s) list: 0-87 Thread(s) per core: 2 Core(s) per socket: 22 Socket(s): 2 NUMA node(s): 4 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Gold 6238 CPU @ 2.10GHz Stepping: 7 CPU MHz: 2100.000 CPU max MHz: 3700.0000 CPU min MHz: 1000.0000 BogoMIPS: 4200.00 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 30976K NUMA node0 CPU(s): 0-2,6-8,11-13,17,18,44-46,50-52,55-57,61,62 NUMA node1 CPU(s): 3-5,9,10,14-16,19-21,47-49,53,54,58-60,63-65 NUMA node2 CPU(s): 22-24,28-30,33-35,39,40,66-68,72-74,77-79,83,84 NUMA node3 CPU(s): 25-27,31,32,36-38,41-43,69-71,75,76,80-82,85-87 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single intel_ppin mba tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local ibpb ibrs stibp dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req pku ospke avx512_vnni arch_capabilities ssbd /proc/cpuinfo cache data cache size : 30976 KB From numactl --hardware WARNING: a numactl 'node' might or might not correspond to a physical chip. available: 4 nodes (0-3) node 0 cpus: 0 1 2 6 7 8 11 12 13 17 18 44 45 46 50 51 52 55 56 57 61 62 node 0 size: 192090 MB node 0 free: 191821 MB node 1 cpus: 3 4 5 9 10 14 15 16 19 20 21 47 48 49 53 54 58 59 60 63 64 65 node 1 size: 193521 MB node 1 free: 193201 MB node 2 cpus: 22 23 24 28 29 30 33 34 35 39 40 66 67 68 72 73 74 77 78 79 83 84 node 2 size: 193521 MB node 2 free: 193014 MB node 3 cpus: 25 26 27 31 32 36 37 38 41 42 43 69 70 71 75 76 80 81 82 85 86 87 node 3 size: 193489 MB node 3 free: 193021 MB node distances: node 0 1 2 3 0: 10 11 21 21 1: 11 10 21 21 2: 21 21 10 11 3: 21 21 11 10 From /proc/meminfo MemTotal: 791166112 kB HugePages_Total: 0 Hugepagesize: 2048 kB From /etc/*release* /etc/*version* os-release: NAME="SLES" VERSION="15" VERSION_ID="15" PRETTY_NAME="SUSE Linux Enterprise Server 15" ID="sles" ID_LIKE="suse" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:15" uname -a: Linux linux-aixk 4.12.14-23-default #1 SMP Tue May 29 21:04:44 UTC 2018 (cd0437b) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Aug 19 09:06 SPEC is set to: /home/cpu2017 Filesystem Type Size Used Avail Use% Mounted on /dev/sdb6 xfs 45G 13G 33G 28% /home Additional information from dmidecode follows. WARNING: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Cisco Systems, Inc. B200M5.4.0.4b.0.0407191258 04/07/2019 Memory: 24x 0xCE00 M393A4K40CB2-CVF 32 GB 2 rank 2933, configured at 2934 (End of data from sysinfo program) Compiler Version Notes ---------------------- ============================================================================== C | 500.perlbench_r(base) 502.gcc_r(base) 505.mcf_r(base) | 525.x264_r(base) 557.xz_r(base) ------------------------------------------------------------------------------ Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.4.227 Build 20190416 Copyright (C) 1985-2019 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C++ | 520.omnetpp_r(base) 523.xalancbmk_r(base) 531.deepsjeng_r(base) | 541.leela_r(base) ------------------------------------------------------------------------------ Intel(R) C++ Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.4.227 Build 20190416 Copyright (C) 1985-2019 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran | 548.exchange2_r(base) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.4.227 Build 20190416 Copyright (C) 1985-2019 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ Base Compiler Invocation ------------------------ C benchmarks: icc -m64 -std=c11 C++ benchmarks: icpc -m64 Fortran benchmarks: ifort -m64 Base Portability Flags ---------------------- 500.perlbench_r: -DSPEC_LP64 -DSPEC_LINUX_X64 502.gcc_r: -DSPEC_LP64 505.mcf_r: -DSPEC_LP64 520.omnetpp_r: -DSPEC_LP64 523.xalancbmk_r: -DSPEC_LP64 -DSPEC_LINUX 525.x264_r: -DSPEC_LP64 531.deepsjeng_r: -DSPEC_LP64 541.leela_r: -DSPEC_LP64 548.exchange2_r: -DSPEC_LP64 557.xz_r: -DSPEC_LP64 Base Optimization Flags ----------------------- C benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=4 -L/usr/local/IntelCompiler19/compilers_and_libraries_2019.4.227/linux/compiler/lib/intel64 -lqkmalloc C++ benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=4 -L/usr/local/IntelCompiler19/compilers_and_libraries_2019.4.227/linux/compiler/lib/intel64 -lqkmalloc Fortran benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=4 -nostandard-realloc-lhs -align array32byte -L/usr/local/IntelCompiler19/compilers_and_libraries_2019.4.227/linux/compiler/lib/intel64 -lqkmalloc The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2017/flags/Intel-ic19.0u1-official-linux64.2019-07-09.html http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.2019-07-31.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2017/flags/Intel-ic19.0u1-official-linux64.2019-07-09.xml http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.2019-07-31.xml SPEC CPU and SPECrate are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ---------------------------------------------------------------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact info@spec.org. Copyright 2017-2020 Standard Performance Evaluation Corporation Tested with SPEC CPU(R)2017 v1.0.2 on 2019-08-19 12:11:15-0400. Report generated on 2020-07-02 17:55:36 by CPU2017 text formatter v6255. Originally published on 2019-09-06.