SPEC CPU2017 Platform Settings for Supermicro Systems

Firmware / BIOS / Microcode Settings

ENERGY_PERF_BIAS_CFG mode:

This BIOS option allows for processor performance and power optmization. Available settings are:

• Extreme Performance: This mode will raise system performance to its highest potential. With Extreme Performance enabled, power consumption will increase as the processor frequency is maximized. In other words, system performance is gained at the cost of system power efficiency, depending on the workload.
• Performance: High performance with less need for power saving.
• Balanced Performance (Default Setting): Provides optimal performance efficiency.
• Balanced Energy: Provides optimal power efficiency.
• Energy Efficient: High power saving with less need for performance.

Power Techonology:

Switch processor power management features. If value "Custom" is set, Customer can define the values of all power management setup items.

Power Performance Tuning:

Allows the OS or BIOS to control the Energy Performance Bias.

Patrol Scrub:

Enable or disable the ability to proactively search the system memory, repairing correctable errors.

CPU C6 Report:

Allows the BIOS to report the CPU C6 State (ACPI C3) to the operating system. During the CPU C6 State, the power to all cache is turned off.

Hyper-Threading (ALL):

Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology). When Disabled only one thread per enabled core is enabled.

Enforce POR:

Enable to enforce Plan Of Record restrictions for DDR4 frequency and voltage programming. Memory speeds will be capped at Intel guidelines. Disabling allows user selection of additional supported memory speeds.

Memory Frequency:

Selects desired memory frequecy (within populated memory limits).

Intel Virtualization Technology:

When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology

Hardware P-states:

This setting allows the user to select between OS and hardware-controlled P-states. Selecting Native Mode allows the OS to choose a P-state. Selecting Out of Band Mode allows the hardware to autonomously choose a P-state without OS guidance. Selecting Native Mode with No Legacy Support functions as Native Mode with no support for older hardware.

SNC (Sub NUMA Cluster):

Sub-NUMA Clusters (SNC) is a feature that provides similar localization benefits as Cluster-On-Die (COD), without some of COD's downsides. SNC breaks up the LLC into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. SNC improves average latency to the LLC.

IMC Interleaving:

This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs). If 2 iMCs are 2-way interleaved, the channel population behind both iMCs must be identical. For iMCs in 1-way interleave, there are no requirements for matching across iMCs.

LLC dead line alloc:

In the Skylake-SP non-inclusive cache scheme, MLC evictions are filled into the LLC. When lines are evicted from the MLC, the core can flag them as "dead" (i.e., not likely to be read again). The LLC has the option to drop dead lines and not fill them in the LLC. If the Dead Line LLC Alloc feature is disabled, dead lines will always be dropped and will never fill into the LLC. This can help save space in the LLC and prevent the LLC from evicting useful data. However, if the Dead Line LLC Alloc feature is enabled, the LLC can opportunistically fill dead lines into the LLC if there is free space available.

Stale AtoS:

The in-memory directory has three states: I, A, and S. I (invalid) state means the data is clean and does not exist in any other socket's cache. The A (snoopAll) state means the data may exist in another socket in exclusive or modified state. S (Shared) state means the data is clean and may be shared across one or more socket's caches. When doing a read to memory, if the directory line is in the A state we must snoop all the other sockets because another socket may have the line in modified state. If this is the case, the snoop will return the modified data. However, it may be the case that a line is read in A state and all the snoops come back a miss. This can happen if another socket read the line earlier and then silently dropped it from its cache without modifying it. If Stale AtoS feature is enabled, in the situation where a line in A state returns only snoop misses, the line will transition to S state. That way, subsequent reads to the line will encounter it in S state and not have to snoop, saving latency and snoop bandwidth. Stale AtoS may be beneficial in a workload where there are many cross-socket reads.

LLC prefetch:

The LLC prefetcher is an additional prefetch mechanism on top of the existing prefetchers that prefetch data into the core Data Cache Unit (DCU) and Mid-Level Cache (MLC). Enabling LLC prefetch gives the core prefetcher the ability to prefetch data directly into the LLC without necessarily filling into the MLC.

XPT prefetch:

This feature allows an LLC read request to be speculatively duplicated and sent concurrently to the appropriate MC (Memory Controller). These speculative MC reads are sent when an LLC miss is likely based on recent LLC history. IIf an LLC miss does occur, the MC read is already in flight so the requested data will be returned more quickly.

SDDC Plus One:

Which is the enhanced feature to SDDC, will spare the faulty DRAM device out after an SDDC event has occurred. After the event, the SDDC+1 ECC mode is activated to protect against any additional memory failure caused by a ‘single-bit’ error in the same memory rank.

ADDDC Sparing:

Which is an improved feature of ADDDC, will allow the error correction code to correct an error caused by the failure of two DRAM devices or by a single-bit error that is beyond a device failure in the lockstep mode. ADDDC+1 will not issue a performance penalty before a device fails. Please note that virtual lockstep mode will only start to work for ADDDC after a faulty DRAM module is spared out at Bank granularity or Rank granularity.