SPEC CPU2017 Flag Description for NEC Server Platform
cpupower frequency-set:
cpupower utility is a collection of tools for power efficiency of processor.
frequency-set sub-command controls settings for processor frequency.
"-g [governor]" specifies a policy to select processor frequency.
The performance governor statically sets frequency of the processor cores specified
by "-c" option to the highest possible for maximum performance.
nohz_full:
This kernel option sets adaptive tick mode (NOHZ_FULL) to specified processors.
Since the number of interrupts is reduced to ones per second, latency-sensitive
applications can take advantage of it.
numa_balancing:
This OS setting controls automatic NUMA balancing on memory mapping and process placement.
Setting 0 disables this feature. It is enabled by default (1).
irqbalance:
Disabled through "service irqbalance stop". Depending on the workload involved, the irqbalance service reassigns various IRQ's to system CPUs. Though this service might help in some situations, disabling it can also help environments which need to minimize or eliminate latency to more quickly respond to events.
Tuning Kernel parameters:
The following Linux Kernel parameters were tuned to better optimize performance of some areas of the system:
- vm.dirty_background_ratio: Set through "echo 40 > /proc/sys/vm/dirty_background_ratio". This setting can help Linux disk caching and performance by setting the percentage of system memory that can be filled with dirty pages.
- vm.dirty_ratio: Set through "echo 40 > /proc/sys/vm/dirty_ratio". This setting is the absolute maximum amount of system memory that can be filled with dirty pages before everything must get committed to disk.
Memory RAS Mode:
This server has "SDDC Mode","ADDDC Mode", "Spare Mode", "Full Mirror Mode", "Addr Mirror Mode", "Reliable Memory Mode", and "Memory Scrubbing Function" as memory RAS functions.
This default setting is "ADDDC Mode".
- SDDC Mode:The SDDC Mode is supporting SDDC (Single Device Data Correction) which does an error correction to ECC correction (64bit Data+8bit ECC) and one DRAM breakdown.
The memory performance is excellent compared with ADDDC Mode of (2) in SDDC.
When installing DIMM which installs RAM of x4 bit, ECC correction and SDDC are supported.
When installing DIMM which installs RAM of x8 bit, SDDC isn't supported.
When installing DIMM which installs RAM of x8 bit, only ECC correction is supported.
- ADDDC Mode:The ADDDC Mode is supporting DDDC (Double Device Data Correction) which does an error correction to ECC correction (64bit Data+8bit ECC) and 2 DRAM breakdowns. A RAS function is excellent compared with SDDC Mode of (1) in ADDC.
When installing DIMM which installs RAM of x4 bit, ECC correction and ADDDC are supported.
When installing DIMM which installs RAM of x8 bit, ADDDC isn't supported.
When installing DIMM which installs RAM of x8 bit, only ECC correction is supported.
- Spare Mode:Spare Mode is a function that operates with a spare rank and continues processing by copying and replacing data to the spare rank on the same channel when any error signs are detected in the rank that is in operation.
The RAS function is excellent compared with SDDC Mode of (1) and ADDDC Mode of (2), from the memory into which OS loaded the available memory capacity, spare Rank, that, it decreases.
When loading DIMM which loads RAM of x4 bit make-up, the spare Rank function, ECC correction (64bit Data+8bit ECC) and SDDC are supported.
When installing DIMM which installs RAM of x8 bit, SDDC isn't supported.
When installing DIMM which installs RAM of x8 bit, support supports the spare Rank function and ECC correction.
- Full Mirror Mode:In full mirror mode, operations are carried out by installing mirroring memory, memory contents are completely duplicated (mirrored) always in the mirroring memory, and when memory failures are detected, the process is continued by switching to the mirroring memory.
The RAS function is excellent compared with SDDC Mode of (1), ADDDC Mode of (2) and Spare Mode of (3), but OS decreases in half of the memory capacity into which the available memory capacity was loaded.
The mirroring memory function and ECC correction (64bit Data+8bit ECC) are supported with a case of both of the occasion equipped with DIMM which loads RAM of x4 bit and the occasion equipped with DIMM which installs RAM of x8 bit.
- Addr Mirror Mode:Addr Mirror Mode duplicates (mirrors) 4 GB or less area where the Linux kernel is located to the mirroring memory, and when memory failures are detected, this function continues the process by correcting the error with the information that was mirrored.
The memory by which a mirroring is done is limited compared with Full Mirror Mode of (4), but it's excellent in use efficient aspect of a memory because OS will be only the territory minute when the available memory capacity is decreased by a mirroring.
The mirroring memory function and ECC correction (64bit Data+8bit ECC) are supported with a case of both of the occasion equipped with DIMM which installs RAM of x4 bit and the occasion equipped with DIMM which loads RAM of x8 bit.
- Reliable Memory Mode:Reliable Memory Mode has three modes (Hypervisor Memory Mirroring, Partial Memory Mirroring, and Whole Memory Mirroring).
Hypervisor Memory Mirroring and Partial Memory Mirroring duplicate (mirror) the area of the VMware kernel or the virtual machine and place in the mirroring memory, and when memory failures are detected, corrects the error with the information that was mirrored and continues the process.
Hypervisor Memory Mirroring mirrors 9 GB of memory per processor. If you want to mirror the VMware kernel, please select this mode. Partial Memory Mirroring mirrors 1/4 the memory size installed for each processor. Please select this mode if you want to mirror VMware kernel and virtual machine. Since mirroring of the virtual machine depends on the size of the mirrored area, select Whole Memory Mirroring to mirror all the virtual machines.
Compared to Whole Memory Mirroring, the Mirroring area is limited in Hypervisor Memory Mirroring and Partial Memory Mirroring, but is excellent in terms of memory usage efficiency as the reduction in the memory capacity available for the OS is only the mirrored area.
Whole Memory Mirroring is the function that always duplicates all memory contents in mirroring memory and continues processing by switching to mirroring memory when memory failure is detected as well as (4) Full Mirror Mode.
Whole Memory Mirroring can mirror VMware kernel and all virtual machines by mirroring whole memory in the system.
The RAS function in Whole Memory Mirroring is superior compared to Hypervisor Memory Mirroring, Partial Memory Mirroring, but the available memory capacity for the OS is reduced to half of the installed memory capacity.
The mirroring memory function and ECC correction (64bit Data+8bit ECC) are supported with a case of both of the occasion equipped with DIMM which installs RAM of x4 bit and the occasion equipped with DIMM which loads RAM of x8 bit.
- Memory Scrubbing Feature:The server is provided with patrol scrubbing and demand scrubbing functions.
- Patrol scrubbing function
Periodically accesses system memory and when correctable errors such as single bit errors are detected, the data is corrected and written back the memory, restoring the memory to the error-free state.
- Demand scrubbing function
When correctable errors such as a single bit error is detected during memory access when the operations are being processed, the corrected data is written back to the memory, restoring the memory to the error-free state.
By correcting errors in advance, the possibility of uncorrectable errors being generated can be reduced.
VT-x:
Enable or disable the processor virtualization feature which improve virtualization performance and scalabilities.
This option is inaccessible when Intel TXT is set to enabled.
This default setting is "Enabled".
- Disabled: Disables the function.
- Enabled : Enables the function.
Processor C6 Report:
Set Enable/Disable of the C6 State transition function by OS.
This default setting is "Enabled".
- Disabled: Disables the function.
- Enabled: Transition to C6 State (Deep Power Down: Stop power supply to other than SRAM), depending on the load condition of the processor, to reduce energy consumption while maintaining optimum performance.
DCU Streamer Prefetcher:
Set [enable / disable] of DCU Streamer Prefetcher of processor.
This default setting is "Enabled".
- Disabled: Disables the function.
- Enabled: Analyzes the cache access pattern and prefetches the most relevant data in the L1 cache. As a result, performance may be improved.
OS Performance Tuning:
OS Performance Tuning is the setting which enables or disables the OS power management policy.
If enabled, the processor power/performance is controlled by OS.
If disabled, "Energy Performance" is displayed and the processor power/performance is controlled by "Energy Performance" setting in the BIOS.
This default setting is "Enabled".
- Disabled: Disables the function.
- Enabled : Enables the function.
Energy Performance:
Set the operation of the processor to performance priority or power saving priority. This item is displayed only when 'OS Performance Tuning' is set to Disabled.
This default setting is "Balanced Performance".
- Performance:
It is set to Performance priority.
- Balanced Performance:
This setting is balanced between performance and power saving. Performance takes precedence over Balanced Energy.
- Balanced Energy:
This setting is balanced between performance and power saving. Power saving takes precedence over Balanced Performance.
- Energy Efficient:
Power saving is a top priority.
Dead Line LLC Allocation:
In the Skylake non-inclusive cache scheme, mid-level cache (MLC) evictions are filled into the last-level cache (LLC).
If a line is evicted from the MLC to the LLC, the core can flag the evicted MLC lines as "dead." This means that the lines are not likely to be read again.
This option allows dead lines to be dropped and never fill the LLC if this option is disabled.
However, if this option is enabled, the LLC can opportunistically fill dead lines into the LLC if there is free space available.
This default setting is "Enabled".
- Disabled: Disables the function.
- Enabled: Enables the function.
Patrol Scrub:
Activate the patrol scrubbing function.
This default setting is "Enabled".
- Disabled: Disables the function.
- Enable: Memory is accessed periodically, and when a correctable fault is detected, the memory is restored to the error-free state by writing the corrected data back to the memory.
Memory P.E. Retry:
Set [Enable / Disable] for DDR4 CMD / ADDR Parity Error Retry function.
This default setting is "Enabled".
- Disabled: Disables the function.
- Enabled: Performs a retry process when CMD/ADDR Parity Error is detected during memory access. Although this can reduce the occurrence of DRAM failure, the memory access performance may be degraded.
Sub NUMA Clustering (SNC):
SNC breaks up the last level cache (LLC) into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. SNC improves average latency to the LLC and memory. SNC is a replacement for the cluster on die (COD) feature found in previous processor families. For a multi-socketed system, all SNC clusters are mapped to unique NUMA domains.
Set Enable/Disable of Sub NUMA Clustering function.
This item is displayed only when a processor supporting this function is installed.
This default setting is "Disabled".
- Disabled: Disables the function.
- Enabled: Enables the function.