SPEC CPU2006/CPU2017 Platform Settings for M Computers Intel-based systems

Firmware / BIOS / Microcode Settings

Intel(R) Hyper-Threading Tech:

Intel(R) Hyper-Threading Technology allows multithreaded software applications to execute threads in parallel within each processor. Can be [Enabled] or [Disabled].

Active Processor Cores:

Number of cores to enable in each processor package. Can be set from [1] to [all].

Execute Disable Bit:

Can help prevent certain classes of malicious buffer overflow attacks. Can be [Enabled] or [Disabled].

Intel(R) Virtualization Technology:

Allows a platform to run multiple operating systems and applications in independent partitions. Can be [Enabled] or [Disabled].

Enhanced Error Containment Mode:

Enable Enhanced Error Containment Mode(Data Poisoning) - Erroneous data coming from memory will be poisoned. If disabled(default), will be in legacy Mode - No data poisoning support available.

MLC Streamer:

Memory Latency Checker (MLC) Streamer is a speculative prefetch unit within the processor(s). Can be [Enabled] or [Disabled].

MLC Spatial Prefetcher :

[Enabled] Fetches adjacent cache line (128 bytes) when required data is not currently in cache [Disabled] Only fetches cache line with data required by the processor (64 bytes)

L1-data cache (DCU) Data Prefetcher:

[Enabled] The next cache line will be prefetched into L1 data cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data [Disabled] Only fetches cache line with data required by the processor (64 bytes)

L1-data cache (DCU) Instruction Prefetcher:

The next cache line will be prefetched into L1 instruction cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. Can be [Enabled] or [Disabled].

LLC Prefetch:

Last Level Cache (LLC) Prefetcher. Can be [Enabled] or [Disabled].

CPU and Power Performance Policy:

Allows the user to set an overall power and performance policy for the system, and when changed will modify a selected list of options to achieve the policy. These options are still changeable outside of the policy but do reflect the changes that the policy makes when a new policy is selected. [Performance] - Optimization is strongly toward performance, even at the expense of energy efficiency [Balanced Performance] - Weights optimization towards performance, while conserving energy [Balanced Power] - Weights optimization towards energy conservation, with good performance [Power] - Optimization is strongly toward energy efficiency, even at the expense of performance

Workload Configuration:

Controls the aggressiveness of the energy performance BIAS settings. This bit field allows the Basic Input-Output System (BIOS) to choose a configuration that may improve performance on certain workloads. Can be [Balanced] or [I/O Sensitive].

Uncore Frequency Scaling:

Allows the voltage and frequency of Uncore to be programmed independently. The Uncore activity is monitored to optimize the frequency in real-time. Can be [Enabled] or [Disabled].

Performance P-limit:

Allows the Uncore frequency coordination of two processors. Can be [Enabled] or [Disabled].

Enhanced Intel SpeedStep(R) Tech:

Allows the system to dynamically adjust processor voltage and core frequency, which can result in decreased average power consumption and decreased average heat production. Can be [Enabled] or [Disabled].

Intel(R) Turbo Boost Technology:

Allows the processor to automatically increase its frequency if it is running below power, temperature and current specifications. Can be [Enabled] or [Disabled].

Energy Efficient Turbo:

When Energy Efficient Turbo is enabled, the Central Processing Unit (CPU) cores only enter the turbo frequency when the Power Control Unit (PCU) detects high utilization.

CPU C-State:

When Central Processing Unit (CPU) C-State is enabled, the Central Processing Unit (CPU) cores enter the sleep state when there is no loading on it. Can be [Enabled] or [Disabled].

Package C-State:

Set and specifies the lowest C-state for Processor package. [C0/C1 state] - No C-state package support [C2 state] [C6(non Retention) state] [C6(Retention) state] - Provides more power saving than C6 non retention state [No limit] - No C-state package limit

C1E Autopromote:

[Enabled] - the Central Processing Unit (CPU) will switch to the minimum Enhanced Intel SpeedStep(R) Technology operating point when all execution cores enter C1. Frequency will switch immediately, followed by gradual Voltage switching. [Disabled] - the Central Processing Unit (CPU) will not transit to the minimum Enhanced Intel SpeedStep(R) Technology operating point when all execution cores enter C1.

Processor C6:

Processor reports C6 state to Operating System (OS). Can be [Enabled] or [Disabled].

Hardware P-states:

[Disable] - Hardware chooses a P-state based on Operating System (OS) Request (Legacy P-states) [Native Mode] - Hardware chooses a P-state based on Operating System (OS) guidance [Out of Band Mode] - Hardware autonomously chooses a P-state (no Operating System (OS) guidance) [Native Mode with No Legacy Support]

Intel(R) UPI Frequency Select:

Allows for selecting the Intel(R) UltraPath Interconnect (UPI) Frequency. Recommended to leave in [Auto Max] so that the Basic Input-Output System (BIOS) can select the highest common Intel(R) UltraPath Interconnect Frequency. Can be set [8.0GT/s], [9.6GT/s], [10.4GT/s] or [Auto Max].

IMC Interleaving:

Integrated Memory Controller (IMC) interleaving. Can be set [Auto], [1-way interleaving] or [2-way interleaving].

Mirror Mode:

Allows the user to select the Mirror Mode to be applied for the next boot. Two-level memory (2LM) will be hidden when AEPDimm is not present.

ADDDC Sparing:

Can [Enable] or [Disable] Adaptive Double Device Data Correction (ADDDC) Sparing.

Memory sparing:

Can [Enable] or [Disable] Memory Rank Sparing.

NUMA Optimized:

If enabled, the Basic Input-Output System (BIOS) includes Advanced Configuration and Power Interface (ACPI) tables that are required for Non-Uniform Memory Access (NUMA)-aware Operating Systems.

Sub_NUMA Cluster:

When enabled, sub Non-Uniform Memory Access (NUMA) cluster is enabled. If any memory controller has no memory attached, this feature cannot be enabled.

Patrol Scrub:

When enabled, performs periodic checks on memory cells and proactively walks through populated memory space, to seek and correct soft Error Checking and Correcting (ECC) errors.

Memory Correctable Error:

When enabled, allow memory correctable error to trigger System Management Interrupt (SMI) and log into System Event Log (SEL).

Set Fan Profile:

[Performance] Fan control provides primary system cooling before attempting to throttle memory [Acoustic] The system will favor using throttling of memory over boosting fans to cool the system if thermal thresholds are met

Fan PWM Offset:

Valid Offset 0-100. This number is added to the calculated Pulse-Width Modulation (PWM) value to increase Fan Speed.