SPEC CPU2017 Flag Description - Platform settings
- ulimit
-
This sets user limits of system-wide resources and can set the stack size to n kbytes, or unlimited to allow the stack size to
grow without limit. Some common ulimit commands may include:
- ulimit -s [n | unlimited]: Set the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.
- ulimit -l (number): Set the maximum size that can be locked into memory.
- Kernel parameters
-
The following Linux Kernel parameters were set for better optimize performance.
- dirty_ratio: Set through "echo 8 > /proc/sys/vm/dirty_ratio". This setting is the absolute maximum amount of system memory
that can be filled with dirty pages before everything must get committed to disk.
- swappiness: The swappiness value can range from 1 to 100. A value of 100 will cause the kernel to swap out inactive processes
frequently in favor of file system performance, resulting in large disk cache sizes. A value of 1 tells the kernel to only
swap processes to disk if absolutely necessary. This can be set through a command like "echo 1 > /proc/sys/vm/swappiness"
- zone reclaim mode: Zone reclaim allows the reclaiming of pages from a zone if the number of free pages falls below a watermark
even if other zones still have enough pages available. Reclaiming a page can be more beneficial than taking the performance
penalties that are associated with allocating a page on a remote zone, especially for NUMA machines. To tell the kernel to
free local node memory rather than grabbing free memory from remote nodes, use a command like
"echo 1 > /proc/sys/vm/zone_reclaim_mode"
- Free the file system page cache: The command "echo 1> /proc/sys/vm/drop_caches" is used to free up the filesystem page cache.
- ACPI SRAT L3 Cache As NUMA Domain
-
This BIOS switch controls to generate the distance information of each L3 Cache as a NUMA node in ACPI Static Resource Affinity Table
(SRAT). When this feature is enabled, the BIOS will expose L3 Cache information as a NUMA node in SRAT and allow the operating system
to access and use the information to optimize software thread allocation and memory usage.
This feature allows 3 options: "Disabled", "Enabled", and "Auto". Default is "Auto".
- Disabled: BIOS does not report each L3 chache as a NUMA domain to the OS.
- Enabled: BIOS reports each L3 cache as a NUMA domain to the OS.
- Auto: This switch is set automatically.
- APBDIS
-
This BIOS switch enables or disables Algorithm Performance Boost(APB). The processor feature of Application Power Management(APM) will
allows P-states to be defined with higher frequencies but it may cause the performance jitter between the high power state and the low
power state. To reduce the jitter, this feature forces the Infinity Fabric, which is the interconnect inside and outside of CPU chip,
into the fixed high power state. This feature allows 3 options: "0", "1", and "Auto". Default is "Auto".
- 0: Not APBDIS. CPU dynamically switches Infinity Fabric P-state based on the link usage
- 1: APBDIS. CPU selects the fixed Infinity Fabric P-state control
- Auto: This switch is set automatically.
- Fix SOC P-state
-
This BIOS switch limits CPU SOC (uncore) P-states when "APBDIS" is enabled to minimize the variance of the performance. This feature
allows 4 options: "P0", "P1", "P2", "P3", and "Auto". When "Auto" is selected, CPU SOC P-states will be dynamically adjusted.
Selecting a specific P-state forces the SOC into the P-state frequency. Default is "Auto".
- cTDP Control
-
This BIOS switch allows the user can manually configure the switch of "cTDP". This feature allows 2 options: "Manual" and "Auto".
"Manual" enables to customize configurable TDP. "Auto" uses the platform default TDP. Default is "Auto".
- cTDP
-
This BIOS switch configures the maximum power that the CPU will consume, up to the platform power limit. Valid values vary by CPU model.
If a value outside the valid range or the default value of "0" is set, the CPU will automatically adjust the value so that it does fall
within the valid range.
When increasing cTDP, additional power will only be consumed up to the Package Power Limit, which may be less than the cTDP setting.
| Model | Minimum cTDP | Maximum cTDP |
|---|
| EPYC 7763 | 225 | 280 |
| EPYC 7643 | 225 | 240 |
| EPYC 75F3 | 225 | 280 |
| EPYC 7513 | 165 | 200 |
| EPYC 7453 | 225 | 240 |
| EPYC 74F3 | 225 | 240 |
| EPYC 7443 | 165 | 200 |
| EPYC 7343 | 165 | 200 |
| EPYC 72F3 | 165 | 200 |
- Determinism Slider
-
This BIOS switch is for the determinism to control performance and allows 3 options: "Auto", "Power", and "Performance".
"Auto" setting uses default values for deterministic performance control. "Power" setting provides predicable performance across
all processors of the same type. "Power" setting maximizes performance withing the power limits defined by cTDP.
Default is "Auto".
- DRAM Scrub Time
-
This BIOS switch controls the time between DRAM Scrubbing, which cyclically accesses the main memory of the system in the background
regardless of the operating system in order to detect and correct memory errors in a preventive way.
This feature allows 8 options: "Disabled", "1 hour", "4 hours", "8 hours", "16 hours", "24 hours", "48 hours", and "Auto".
"Disabled" option disables the feature of DRAM Scrubbing and it may result in improving the performance under certain circumstances
but increases the probability of discovering memory errors in case of active accesses by the operating system.
Until these errors are correctable, the ECC technology of the memory modules ensures that the system continues to run in a stable way.
However, too many correctable memory errors increase the risk of discovering non-correctable errors, which then result in a system
standstill.
- EDC Control
-
This BIOS switch allows the user can manually configure the switch of "EDC" and "EDC Platform Limit". This feature allows 2 options:
"Manual" and "Auto". "Manual" enables to customize "EDC" and "EDC Platform Limit". "Auto" uses the platform default EDC.
Default is "Auto".
- EDC
-
Electrical Design Current(EDC) indicates the total maximum current capacity in Apms which can be supplied to the socket for a short
time. The default value of EDC is 0 which select the platform default setting and it can be set up to 300 A. Increasing this value
may increase the frequency at the cost of additional power consumption.
- EDC Platform Limit
-
This BIOS switch limit the maximum EDC in watts which the platform can support. The default value is 0 which selects the platform
default setting and it can be set up to 300 W. Increasing this value may increase the frequency at the cost of additional power
consumption.
- Global C-state Control
-
This BIOS switch controls IO based C-state generation and DF C-states. This feature allows 2 options: "Disabled", "Enabled, and "Auto".
Default is "Auto"
- IOMMU
-
This BIOS switch allows enabling or disabling of Input-Output Memory Management Unit(IOMMU) which supports the address translation and
system memory access protection on DMA transfer from I/O devices in the system. This feature allows 3 options: "Auto", "Enabled", and
"Disabled". Default is "Auto".
- L1 Stream HW Prefetcher
-
This BIOS switch allows enabling or disabling of L1 Stream HW Prefetcher. This feature allows 2 options: "Disabled", "Enabled, and
"Auto". Default is "Auto".
- L2 Stream HW Prefetcher
-
This BIOS switch allows enabling or disabling of L2 Stream HW Prefetcher. This feature allows 2 options: "Disabled", "Enabled, and
"Auto". Default is "Auto".
- NUMA nodes per socket
-
This BIOS switch specifies the number of desired NUMA nodes per populated socket in the system. This feature allows 5 options:
"NPS0", "NPS1", "NPS2", "NPS4", and "Auto". Default is "Auto".
- NPS0: All physical processor is a NUMA node and memory accesses are interleaved across all memory channels of two sockets together.
- NPS1: Each physical processor is a NUMA node, and memory accesses are interleaved across all memory channels
directly connected to the physical processor.
- NPS2: Each physical processor is two NUMA nodes, and memory accesses are interleaved across 4 memory channels.
- NPS4: Each physical processor is four NUMA nodes, and memory accesses are interleaved across 2 memory channels.
- Auto: Use default value. Current default is NPS1
- Package Power Limit Control
-
This BIOS switch configures a per CPU Package Power Limit value applicable for all populated CPUs in the system. This feature allows 2
options: "Manual" and "Auto". "Manual" set customized configurable Package Power Limit. "Auto" uses the platform default Package Power
Limit.
- Package Power Limit
-
This BIOS switch specifies the maximum power that each CPU package may consume in the system. The actual power is limited by the maximum
setting of both the "Package Power Limit" and "cTDP".
- SMT Control
-
This BIOS switch allows enabling or disabling of symmetric multithreading on processors. This feature allows 3 options: "Disabled",
"Enabled", and "Auto". When "Enabled" is set, each physical processor core operates as two logical processor cores. When "Disabled"
is set, each physical core operates as only one logical processor core.
"Auto" enables this feature and can improve overall performance for applications that benefit from a higher processor core count.
Default is "Auto".
- SVM Mode
-
This BIOS switch is for CPU virtualization function. With SVM enabled virtual machines can be installed on the system.
This feature allows 2 options: "Enabled" and "Disabled". Default is "Enabled".
- xGMI Link Max Speed
-
This BIOS switch controls the maximum link speed of GMI (Global Memory Interface) which is the socket-to-socket interconnection.
Limitting the maximum link speed can reduce xGMI power consumption and increaces the available power for cores which may improve
the performance in workloads which aware NUMA. The default setting is "Auto" which selects the maximum link speed per CPU model.
- 10.667Gbps
- 11Gbps
- 12Gbps
- 13Gbps
- 14Gbps
- 15Gbps
- 16Gbps
- 17Gbps
- 18Gbps
- 19Gbps
- 20Gbps
- 21Gbps
- 22Gbps
- Auto