SPEC CPU2017 Flag Description - Platform settings
- cpupower frequency-set
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cpupower utility is a collection of tools for power efficiency of processor.
frequency-set sub-command controls settings for processor frequency.
"-g [governor]" specifies a policy to select processor frequency.
The performance governor statically sets frequency of the processor cores specified
by "-c" option to the highest possible for maximum performance.
- cpupower idle-set
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idle-set sub-command of cpupower utility controls a processor idle state (C-state) of
the kernel. "-d [state_no]>" option disables a specific processor idle state.
Disabling idle state can reduce the idle-wakeup delay, but it results in substantially
higher power consumption. By default, processor idle states of all CPU cores are set.
- isolcpus
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This kernel option excludes a specified processor from load balancing by the kernel
scheduler. This prevents the scheduler from scheduling any user-space threads on
this processor.
- nohz_full
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This kernel option sets adaptive tick mode (NOHZ_FULL) to specified processors.
Since the number of interrupts is reduced to ones per second, latency-sensitive
applications can take advantage of it.
- numa_balancing
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This OS setting controls automatic NUMA balancing on memory mapping and process placement.
Setting 0 disables this feature. It is enabled by default (1).
- sched_min_granularity_ns
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This OS setting controls the minimal preemption granularity for CPU bound tasks.
As the number of runnable tasks increases, CFS(Complete Fair Scheduler), the scheduler
of the Linux kernel, decreases the timeslices of tasks. If the number of runnable
tasks exceeds sched_latency_ns/sched_min_granularity_ns, the timeslice becomes
number_of_running_tasks * sched_min_granularity_ns. The default value is 8000000(ns).
- sched_wakeup_granularity_ns
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This OS setting controls the wake-up preemption granularity. Increasing this variable
reduces wake-up preemption, reducing disturbance of compute bound tasks.
Lowering it improves wake-up latency and throughput for latency critical tasks,
particularly when a short duty cycle load component must compete with CPU bound components.
The default value is 10000000 (ns).
- Adjacent Cache Line Prefetch
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This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
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This prefetcher always collects cache line pairs (128 bytes) from the main memory,
providing that the data is not already contained in the cache. If this prefetcher is
disabled, only one chace line (64 bytes) is collected, which contains the data required
by the processor.
- CPU C1E Support
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Enabling this option which is the default allows the processor to transmit to its
minimum frequency when entering the power state C1. If the switch is disabled the
CPU stays at its maximum frequency in C1. Because of the increase of power
consumption users should only select this option after performing application
benchmarking to verify improved performance in their environment.
- DCU Ip Prefetcher
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This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
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This L1-cache prefether looks for sequential load history and attempts on this basis to
determine the next data to be expected and, if necessary, to prefetch this data from the
L2 cache or the main memory into the L1 cache.
- DCU Streamer Prefetcher
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This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
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This prefetcher is a L1 data cache prefetcher, which detects multiple loads from the same cache line
done within a time limit, in order to then prefetch the next line from the L2 cache or the main memory
into the L1 cache based on the assumption that the next cache line will also be needed.
- DDR4 Write Data CRC Protection
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This BIOS switch allows 2 options: "Enabled" and "Disabled".
The default setting is "Enabled" (PRIMERGY servers) or "Disabled" (PRIMEQUEST servers).
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This BIOS option enables or disable DDR4 CRC write feature. When "Enabled" is selected,
memroy controller generates a CRC code from the data to write.
- Energy Performance:
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This BIOS switch allows 4 options: "Balanced performance", "Performance",
"Balanced Energy" and "Energy Efficient". The default is "Balanced Performance"
optimized to maximum power savings with minimal impact on performance.
"Performance" disables all power management options with any impact on performance.
"Balanced Energy" is optimized for power efficiency and "Energy Efficient" for
power savings. The BIOS switch is only selectable if the BIOS switch
"Power Technology" is selectable and set to "Custom".
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The two options "Balanced Performance" and "Balanced Energy" should always be the
first choice as both options optimize the efficiency of the system. In cases where
the performance is not sufficient or the power consumption is too high the two
options "Performance" or "Energy Efficient" could be an alternative.
- Fan Control
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This BIOS switch allows 2 options: "Auto" and "Full".
The default setting is "Auto", which allows the system to control the fan speed according to
the system temperature. If "Full" is selected, the system runs fans at 100% speed and it may
improve the system performance. But it increases the power consumption of the system.
- IMC Interleaving
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This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs).
There are two IMCs per socket in Skylake Server. If IMC Interleaving is set to 2-way,
addresses will be interleaved between the two IMCs. If IMC Interleaving is set to 1-way,
there will be no interleaving. If SNC is disabled, IMC Interleaving should be set to 2-way.
If SNC is enabled, IMC Interleaving should be set to 1-way.
Default setting is "Auto".
- Intel Virtualization Technology
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This BIOS option enables or disables additional virtualization functions of the CPU.
If the server is not used for virtualization, this option should be set to "Disabled".
This can result in energy savings. Default setting is "Enabled".
- IO Directory Cache (IODC)
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This BIOS switch allows 2 options: "Auto" and "Disabled". The default is "Auto".
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IODC eliminates directory cache reads for remote IO writes and reduces access overhead
to directory cache. This feature improves stream throughput.
- Hardware Prefetcher
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This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
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This prefetcher looks for data streams on the assumption that if the data is requested at
address A and A+1, the data will also presumably be required at address A+2. This data is
then prefetched into the L2 cache from the main memory.
- HWPM Support
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This BIOS switch allows 4 options: "Native Mode", "Disabled", "Out of Band Mode"
and "Native Mode with No legacy Support". The default is "Native Mode".
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With Hardware Power Management(HWPM) the processors provides a flexible interface
between Hardware and Platform for performance management and improving energy efficiency.
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In Native Mode the HWPM operates cooperatively with the OS via a software interface
to provide constraints and hints.
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When disabled, system does not use HWPM.
- Hyper-Threading
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This BIOS option enables or disables additional hardware thread which shares same
physical core. Generally "Enabled" is recommended but disabling it makes sense
for the application which requires the shortest possible response times.
Default setting is "Enabled".
- Link Frequency Select
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This switch allows the configuration of the Intel Ultra Path Interconnect (UPI)
link speed. Default is auto, which configures the optimal link speed automatically.
It can be set "9.6 GT/s", "10.4 GT/s" or "Auto".
- Max Page Table Size Select
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This BIOS switch allows 2 options: "2M" adn "1G". The default is "1G".
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This switch selects maximum page table size to use in virtual memory system of OS.
- LLC Dead Line Alloc
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This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
In the Cascadelake non-inclusive cache scheme, the mid-level cache (MLC) evictions are filled
into the last-level cache (LLC). When lines are evicted from the MLC, the core can flag them
as "dead" (i.e., not likely to be read again).
The LLC has the option to drop dead lines and not fill them in the LLC.
If the Dead Line LLC Alloc feature is disabled, dead lines will always be dropped and will
never fill into the LLC. This can help save space in the LLC and prevent the LLC from evicting
useful data. However, if the Dead Line LLC Alloc feature is enabled, the LLC can
opportunistically fill dead lines into the LLC if there is free space available.
- LLC Prefetcher
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This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
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This option configures the processor last level cache (LLC) prefetch feature as a result of the
non-inclusive cache architecture. The LLC prefetcher exists on top of other pfrefetchers that can
prefetch data into the core data cache unit(DCU) and mid-level cache (MLC).
In some cases, setting this option to disabled can improve performance.
Typically, setting this option to enable provides better performance.
If this prefetcher is enabled, the core can prefetch data directly to the LLC and if disabled,
the other core prefetchers are unaffected.
- Local/Remote Threshold
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This BIOS switch allows 5 options: "Disable", "Auto", "Low", "Medium", and "High".
PRIMEQUEST servers doen't have options of "Disable", "Medium", and "High".
The default is "Auto".
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This BIOS option changes the threshold number of requests in remote/local-to-remote request queues
to cause the throttling.
- Override OS Energy Performance
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This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Disabled".
The power control unit (PCU) in the processors takes on the central role of controlling
the energy-saving options. The PCU can be parameterized in order to consequently control
the settings more in the direction of energy efficiency or in the direction of maximum
performance.
The default setting allows you to control energy-saving options through the operating
system by its power plan. If enabled, PCU overrides the setting of the operating system
and controls the energy-saving options based on the settings in the BIOS.
- P-State Coordination
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This BIOS switch allows 3 options: "HW_ALL", "SW_ALL", and "SW_ANY". The default is "HW_ALL".
This switch controls how BIOS communicates the P-state support model to the operating system.
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If this switch is set to "HW_ALL", the processor hardware is responsible for coodinating the
P-state among logical processors in a package. If this is set to "SW_ALL", operating system
power management is responsible for coordinating P-state among logical processors and must
initiate the transition on all of the logical processors. And if "SW_ANY" is selected,
operating system power management is responsible for coordinating the P-state among logical
processors and may initiate the transistion on any of the logical processors in the domain.
- Package C State limit
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This BIOS option allows 6 options: "C0", "C2", "C6", "C6(Retention)", "No Limit" and "Auto".
The default setting is "Auto".
Package C-states is one of energy-saving options of the processor, which not only allow
the individual cores of a processor, but the entire processor chip to be put into a type
of sleep state. As a result, power consumption is even further reduced.
But the "waking-up time" that is required to change from the lower package C-states to
the active (C0) state is even longer in comparison with the CPU or core C-states.
If the "C0" setting is made in the BIOS, the processor chip always remains active.
It can improve the performance of latency sensitive workloads.
- Patrol Scrub
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This BIOS option enables or disables the so-called memory scrubbing, which cyclically
accesses the main memory of the system in the background regardless of the operating
system in order to detect and correct memory errors in a preventive way. The time of
this memory test cannot be influenced and can under certain circumstances result in
losses in performance. The disabling of the Patrol Scrub option increases the
probability of discovering memory errors in case of active accesses by the operating
system. Until these errors are correctable, the ECC technology of the memory modules
ensures that the system continues to run in a stable way. However, too many correctable
memory errors increase the risk of discovering non-correctable errors, which then
result in a system standstill.
- Power Technology
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This BIOS switch allows 3 options: "Disabled", "Energy Efficient" and "Custom".
The default setting is "Energy Efficient" (PRIMERGY CX servers), or "Custom"
(PRIMEQUEST servers).
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The BIOS option "Power Technology" is a superset of different BIOS options, which
control the performance and power management functions of the processors. In order
to see and individually set the corresponding relevant options, select the setting
"Custom".
- Stale AtoS (Directory AtoS)
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This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Disabled".
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The in-memory directory has three states: I, A, and S.
I (invalid) state means the data is clean and does not exist in any other socket's cache.
A (snoopAll) state means the data may exist in another socket in exclusive or modified state.
S (Shared) state means the data is clean and may be shared across one or more socket's caches.
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When doing a read to memory, if the directory line is in the A state we must snoop all the
other sockets because another socket may have the line in modified state. If this is the case,
the snoop will return the modified data. However, it may be the case that a line is read in
A state and all the snoops come back a miss. This can happen if another socket read the line
earlier and then silently dropped it from its cache without modifying it.
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If Stale AtoS feature is enabled, in the situation where a line in A state returns only snoop
misses, the line will transition to S state. That way, subsequent reads to the line will
encounter it in S state and not have to snoop, saving latency and snoop bandwidth.
Stale AtoS may be beneficial in a workload where there are many cross-socket reads.
- Sub NUMA Clustering
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Sub NUMA Clustering (SNC) breaks up the last-level cache (LLC) into two disjoint clusters
based on address range, with each cluster bound to one memory controller. SNC improves
average latency to the LLC/memory and is a replacement for the "Cluster On Die" (COD)
feature found in previous processor families.
For a multi-socketed system, all SNC clusters are mapped to unique NUMA domains.
IMC Interleaving must be set to the correct value to correspond with SNC enable/disable.
If SNC and IMC Interleave are both set to Auto, the result will be SNC disabled (only one
cluster per socket) with 2-way IMC interleave. If SNC is set to Enable, IMC Interleave
should be set to 1-way, which will result in two clusters per socket.
The BIOS switch "Sub NUMA Clustering" allows 3 options: "auto", "enabled" and "disabled".
The default setting is "Enabled" (PRIMERGY servers), or "auto" (PRIMEQUEST servers).
- Uncore Frequency Override:
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This BIOS switch allows 4 options: "Disabled", "Maximum", "Nominal", and "Power balanced".
The default is "Disabled" optimized for energy efficiency. "Maximum" sets the uncore frequency
to the fixed maximum uncore frequency available. "Nominal" reduces the uncore frequency
to the nominal value.
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Setting this option to "Maximum" may improve performance but also
increase the power consumption of the system. Users should only select
this option after performing application benchmarking to verify improved
performance in their environment.
- Uncore Frequency Scaling:
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This BIOS switch allows 2 options: "Disabled" and "Enabled".
The default is "Enabled" which sets the uncore frequency to the fixed maximum uncore
frequency available. "Disabled" ensures that the uncore frequency is regulated by CPU itself.
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Default setting of "Enabled" may improve performance but also increase the power consumption
of the system. Users should only select this option after performing application benchmarking
to verify improved performance in their environment.
- UPI Link Frequency Select:
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See "Link Frequency Select".
- UPI Link L0p
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This BIOS switch allows 3 options: "Auto", "Disabled", and "Enabled".
The default setting is "Auto" (PRIMERGY servers) or "Enabled" (PRIMEQUEST servers).
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This switch enables or disables Intel Ultra Path Interconnect (UPI) link L0p state for power
saving.
- UPI Link L1
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This BIOS switch allows 3 options: "Auto", "Disabled", and "Enabled".
The default setting is "Auto" (PRIMERGY servers) or "Enabled" (PRIMEQUEST servers).
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This switch enables or disables Intel Ultra Path Interconnect (UPI) link L1 state for power
saving.
- Utilization Profile:
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This BIOS switch allows 2 options: "Even" and "Unbalanced". The default is "Even"
and the best choice for all workloads utilizing the whole system. In cases where
the utilization is highly concentrated on few resources of the system the
performance of the application could be improved by setting to "Unbalanced".
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Setting this option to "Unbalanced" may improve performance but also
increase the power consumption of the system. Users should only select
this option after performing application benchmarking to verify improved
performance in their environment.
- VT-d
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This BIOS option enables or disables I/O virtualization functions of the CPU.
If the server is not used for virtualization, this option should be set to "Disabled".
Default setting is "Enabled".
- WR CRC Feature Control
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See "DDR4 Write Data CRC Protection".
- XPT Prefetch
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This BIOS switch allows 3 options: "Disabled", "Enabled", and "Auto".
The default is "Enabled".
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The Xtended Prediction Table (XPT) prefetcher exists on top of other prefetchers that can
prefetch data into the DCU, MLC, and LLC. The XPT prefetcher will issue a speculative DRAM
read request in parallel to an LLC lookup. This prefetch bypasses the LLC, saving latency.
In some cases, setting this option to disabled can improve performance. Typically, setting
this option to enable provides better performance.