DCU (Level 1 Data Cache) streamer prefetcher is an L1 data cache prefetcher. Lightly threaded applications and some benchmarks can benefit from having the DCU streamer prefetcher enabled.
Default setting is Enable.
This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit (DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.
Values for this BIOS option can be:
Four UPI links are present between the two sockets of the BullSequana SH20. Each UPI link is power consuming and is not necessary for a well localized benchmark as specCPU
Disabling three out of four links allows power saving at UPI level and increased frequency of the core part of the CPU package
The BIOS setting "Link Disable" is present for all 4 UPI ports of the 2 CPU packages.
This setting can be found in Advanced settings / Socket configuration / Uncore configuration / Uncore Per Socket Configuration / CPU Nb / CPU Nb UPI Port 0-3
Values for this BIOS option can be:
To keep only one link, all settings are set to Yes except CPU 0 UPI Port 0 and CPU 1 UPI Port 1
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