SPEC CPU2017 Platform Settings for ASUSTek Systems

Operating System Tuning Parameters

The OS 'cpupower' utility is used to change CPU power governors settings. Available settings are:
kernel.randomize_va_space (ASLR)
This setting can be used to select the type of process address space randomization. Defaults differ based on whether the architecture supports ASLR, whether the kernel was built with the CONFIG_COMPAT_BRK option or not, or the kernel boot options used.
Possible settings: Disabling ASLR can make process execution more deterministic and runtimes more consistent. For more information see the randomize_va_space entry in the Linux sysctl documentation.
Transparent Hugepages (THP)
THP is an abstraction layer that automates most aspects of creating, managing, and using huge pages. It is designed to hide much of the complexity in using huge pages from system administrators and developers. Huge pages increase the memory page size from 4 kilobytes to 2 megabytes. This provides significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead. Most recent Linux OS releases have THP enabled by default.
THP usage is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/enabled. Possible values: THP creation is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/defrag. Possible values: An application that "always" requests THP often can benefit from waiting for an allocation until those huge pages can be assembled.
For more information see the Linux transparent hugepage documentation.

Firmware / BIOS / Microcode Settings

Determinism Slider:
This BIOS option allows for AGESA determinism to control performance.
cTDP Control:
This BIOS option is for "Configurable TDP (cTDP)", it allows user can set customized value for TDP. Available settings are:
TDP is an acronym for "Thermal Design Power." TDP is the recommended target for power used when designing the cooling capacity for a server. EPYC processors are able to control this target power consumption within certain limits. This capability is referred to as "configurable TDP" or "cTDP." cTDP can be used to reduce power consumption for greater efficiency, or in some cases, increase power consumption above the default value to provide additional performance. cTDP is controlled using a BIOS option.

The default EPYC cTDP value corresponds with the microprocessor's nominal TDP. The default cTDP value is set at a good balance between performance and energy efficiency. The EPYC 7763 cTDP can be reduced as low as 225W, which will minimize the power consumption for the processor under load, but at the expense of peak performance. Increasing the EPYC 7763 cTDP to 280W will maximize peak performance by allowing the CPU to maintain higher dynamic clock speeds, but will make the microprocessor less energy efficient. Note that at maximum cTDP, the CPU thermal solution must be capable of dissipating at least 280W or the EPYC 7763 processor might engage in thermal throttling under load.

The available cTDP ranges for each EPYC model are in the table below:
ModelMinimum cTDPMaximum cTDP
EPYC 7763225280
EPYC 7713225240
EPYC 7713P225240
EPYC 7643225240
EPYC 75F3225280
EPYC 7543225240
EPYC 7543P225240
EPYC 7513165200
EPYC 74F3225240
EPYC 7413165200
EPYC 7343165200
EPYC 7313155180
EPYC 7313P155180
EPYC 72F3165200
* cTDP must remain below the thermal solution design parameters or thermal throttling could be frequently encountered.
Power phase shedding:
Power phase shedding allows efficiency optimization of the voltage regulator across the variety of loads, minimizing average energy consumption by optimizing the powertrain for specific load power states. Values for this BIOS option can be: Enabled/Disabled. Current default is Enabled.
SVM Mode:
This is CPU virtualization function. With SVM enabled you'll be able to install a virtual machine on your system. Values for this BIOS option can be: Enabled/Disabled. Current default is Enabled.
SR-IOV support:
In virtualization, single root input/output virtualization or SR-IOV is a specification that allows the isolation of the PCI Express resources for manageability and performance reasons. A single physical PCI Express can be shared on a virtual environment using the SR-IOV specification. If system has SR-IOV capable PCIe Devices, this option Enables or Disables Single Root IO Virtualization Support. Values for this BIOS option can be: Enabled/Disabled. Current default is Disabled.
DRAM Scrub time:
DRAM scrubbing is a mechanism for the memory controller to periodically read all memory locations and write back corrected data. The time interval for scrubbing the entire memory can be: Disabled/1 hour/4 hours/8 hours/16 hours/24 hours/48 hours/Auto. Current default is Auto(AGESA default value).
NUMA nodes per socket:
Specifies the number of desired NUMA nodes per populated socket in the system: Current default is Auto.
Application Power Management (APM) allows the processor to provide maximum performance while remaining within the specified power delivery and removal envelope. APM dynamically monitors processor activity and generates an approximation of power consumption. If power consumption exceeds a defined power limit, a P-state limit is applied by APM hardware to reduce power consumption. APM ensures that average power consumption over a thermally significant time period remains at or below the defined power limit. Set APBDIS=1 will disable Data Fabric APM and the SOC P-state will be fixed. Available settings are:
Fix SOC P-state:
To minimize variance or trade-off memory latency versus bandwidth, algorithm performance boost (APBDIS) can be set and specific hard-fused Data Fabric (SoC) P-states forced for optimized workloads sensitive to latency or throughput. Available settings are:
ACPI SRAT L3 Cache as NUMA Domain:
Each L3 Cache will be exposed as a NUMA node when enabling ACPI SRAT L3 Cache as a NUMA node. On a dual processor system, with up to 8 L3 Caches per processor, this setting will expose 16 NUMA domains. Available settings are:
Package Power Limit Control:
This BIOS option allows user can set customized value for processor package power limit(PPT). Available settings are:
DLWM Support:
Dynamic Link Width Management(DLWM) reduces xGMI lane width from x16 to x8 or x2 if xGMI links have limited traffic. DLWM feature is optimized to trade power between CPU core intensive workloads and I/O bandwidth intensiveworkloads. When link activity is above a threshold, DLWM will increase lane width from x8 to x16 at the cost of some delay, because the I/O die must disconnect the links, retrain them at the new speed and release the system back to functionality. Values for this BIOS option can be: Auto/Enabled/Disabled. Current default is Auto.(Use AGESA default value. Current is Enabled.)
Engine Boost:
ASUS individual feature with the power acceleration design to increase CPU over-all performance. Available settings are: disabled(default) and enabled. Enable it could improve performance, but comes with more power consumption.
Package Power Limit:
Set customize processor Package Power Limit (PPT) value to be used on all populated processors in the system. Current default value is 240 = Use the 240W PPT value. ***PPT will be used as the ASIC power limit***
The Input-Output Memory Management Unit(IOMMU) provides several benefits and is required when using x2APIC. Enabling the IOMMU allows devices (such as the EPYC integrated SATA controller) to present separate IRQs for each attached device instead of one IRQ for the subsystem. The IOMMU also allows operating systems to provide additional protection for DMA capable I/O devices. Values for this BIOS option can be: Auto/Enabled/Disabled. Current default is Auto.(Use AGESA default value. Current is Enabled.)