SPEC(R) CINT2006 Summary Dell Inc. PowerEdge R540 (Intel Xeon Silver 4116, 2.10 GHz) Tue Aug 29 01:10:44 2017 CPU2006 License: 55 Test date: Aug-2017 Test sponsor: Dell Inc. Hardware availability: Sep-2017 Tested by: Dell Inc. Software availability: Apr-2017 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 48 620 757 S 400.perlbench 48 618 758 * 400.perlbench 48 618 759 S 401.bzip2 48 1008 460 S 401.bzip2 48 1008 460 * 401.bzip2 48 1017 455 S 403.gcc 48 499 775 S 403.gcc 48 497 778 S 403.gcc 48 498 775 * 429.mcf 48 288 1520 * 429.mcf 48 289 1510 S 429.mcf 48 287 1520 S 445.gobmk 48 774 650 S 445.gobmk 48 774 650 * 445.gobmk 48 776 649 S 456.hmmer 48 298 1510 * 456.hmmer 48 300 1490 S 456.hmmer 48 297 1510 S 458.sjeng 48 834 696 S 458.sjeng 48 835 695 S 458.sjeng 48 835 696 * 462.libquantum 48 95.3 10400 * 462.libquantum 48 95.6 10400 S 462.libquantum 48 95.3 10400 S 464.h264ref 48 894 1190 S 464.h264ref 48 892 1190 * 464.h264ref 48 891 1190 S 471.omnetpp 48 538 558 S 471.omnetpp 48 538 558 S 471.omnetpp 48 538 558 * 473.astar 48 561 601 S 473.astar 48 566 595 S 473.astar 48 565 596 * 483.xalancbmk 48 260 1270 S 483.xalancbmk 48 259 1280 * 483.xalancbmk 48 259 1280 S ============================================================================== 400.perlbench 48 618 758 * 401.bzip2 48 1008 460 * 403.gcc 48 498 775 * 429.mcf 48 288 1520 * 445.gobmk 48 774 650 * 456.hmmer 48 298 1510 * 458.sjeng 48 835 696 * 462.libquantum 48 95.3 10400 * 464.h264ref 48 892 1190 * 471.omnetpp 48 538 558 * 473.astar 48 565 596 * 483.xalancbmk 48 259 1280 * SPECint(R)_rate_base2006 1030 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon Silver 4116 CPU Characteristics: Intel Turbo Boost Technology up to 3.00 GHz CPU MHz: 2100 FPU: Integrated CPU(s) enabled: 24 cores, 2 chips, 12 cores/chip, 2 threads/core CPU(s) orderable: 1,2 chip Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 1 MB I+D on chip per core L3 Cache: 16.5 MB I+D on chip per chip Other Cache: None Memory: 192 GB (12 x 16 GB 2Rx8 PC4-2666V-R, running at 2400 MT/s) Disk Subsystem: 1 x 1 TB SATA 7200 RPM Other Hardware: None SOFTWARE -------- Operating System: SUSE Linux Enterprise Server 12 SP2 4.4.21-69-default Compiler: C/C++: Version 17.0.3.191 of Intel C/C++ Compiler for Linux Auto Parallel: No File System: xfs System State: Run level 3 (multi-user) Base Pointers: 32-bit Peak Pointers: 32/64-bit Other Software: Microquill SmartHeap V10.2 Submit Notes ------------ The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" Platform Notes -------------- BIOS settings: Virtualization Technology disabled System Profile set to Custom CPU Performance set to Maximum Performance C States set to autonomous C1E disabled Uncore Frequency set to Dynamic Energy Efficiency Policy set to Performance Memory Patrol Scrub disabled Logical Processor enabled CPU Interconnect Bus Link Power Management disabled PCI ASPM L1 Link Power Management disabled Sysinfo program /root/cpu2006-1.2_ic17u3/config/sysinfo.rev6993 Revision 6993 of 2015-11-06 (b5e8d4b4eb51ed28d7f98696cbe290c1) running on linux-28u4 Tue Aug 29 01:10:46 2017 This section contains SUT (System Under Test) info as seen by some common utilities. To remove or add to this section, see: http://www.spec.org/cpu2006/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Silver 4116 CPU @ 2.10GHz 2 "physical id"s (chips) 48 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 12 siblings : 24 physical 0: cores 0 1 2 3 4 5 8 9 10 11 12 13 physical 1: cores 0 1 2 3 4 5 8 9 10 11 12 13 cache size : 16896 KB From /proc/meminfo MemTotal: 196687084 kB HugePages_Total: 0 Hugepagesize: 2048 kB /usr/bin/lsb_release -d SUSE Linux Enterprise Server 12 SP2 From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 2 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12-SP2" VERSION_ID="12.2" PRETTY_NAME="SUSE Linux Enterprise Server 12 SP2" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12:sp2" uname -a: Linux linux-28u4 4.4.21-69-default #1 SMP Tue Oct 25 10:58:20 UTC 2016 (9464f67) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Aug 29 00:54 SPEC is set to: /root/cpu2006-1.2_ic17u3 Filesystem Type Size Used Avail Use% Mounted on /dev/sda2 xfs 927G 9.1G 918G 1% / Additional information from dmidecode: Warning: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Dell Inc. 1.0.0 08/10/2017 Memory: 8x 002C00B3002C 18ASF2G72PDZ-2G6D1 16 GB 2 rank 2666 MHz, configured at 2400 MHz 4x 002C0632002C 18ASF2G72PDZ-2G6D1 16 GB 2 rank 2666 MHz, configured at 2400 MHz 4x Not Specified Not Specified (End of data from sysinfo program) General Notes ------------- Environment variables set by runspec before the start of the run: LD_LIBRARY_PATH = "/root/cpu2006-1.2_ic17u3/lib/ia32:/root/cpu2006-1.2_ic17u3/lib/intel64:/root/cpu2006-1.2_ic17u3/sh10.2" Binaries compiled on a system with 1x Intel Core i7-4790 CPU + 32GB RAM memory using Redhat Enterprise Linux 7.2 Transparent Huge Pages enabled by default Filesystem page cache cleared with: shell invocation of 'sync; echo 3 > /proc/sys/vm/drop_caches' prior to run runspec command invoked through numactl i.e.: numactl --interleave=all runspec Base Compiler Invocation ------------------------ C benchmarks: icc -m32 -L/opt/intel/compilers_and_libraries_2017/linux/lib/ia32 C++ benchmarks: icpc -m32 -L/opt/intel/compilers_and_libraries_2017/linux/lib/ia32 Base Portability Flags ---------------------- 400.perlbench: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX_IA32 401.bzip2: -D_FILE_OFFSET_BITS=64 403.gcc: -D_FILE_OFFSET_BITS=64 429.mcf: -D_FILE_OFFSET_BITS=64 445.gobmk: -D_FILE_OFFSET_BITS=64 456.hmmer: -D_FILE_OFFSET_BITS=64 458.sjeng: -D_FILE_OFFSET_BITS=64 462.libquantum: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX 464.h264ref: -D_FILE_OFFSET_BITS=64 471.omnetpp: -D_FILE_OFFSET_BITS=64 473.astar: -D_FILE_OFFSET_BITS=64 483.xalancbmk: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 C++ benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 -Wl,-z,muldefs -L/sh10.2 -lsmartheap Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic17.0-official-linux64-revF.html http://www.spec.org/cpu2006/flags/Dell-Platform-Flags-PowerEdge14G-revC.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2006/flags/Intel-ic17.0-official-linux64-revF.xml http://www.spec.org/cpu2006/flags/Dell-Platform-Flags-PowerEdge14G-revC.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2017 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.2. Report generated on Wed Sep 20 11:02:59 2017 by CPU2006 ASCII formatter v6932. Originally published on 19 September 2017.