ACCEL Flag Description
Lenovo Global Technology ThinkSystem SR655

Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.

• • -O2
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Level-two optimization (-O2 or -O) specifies global optimization. The -fast option generally will specify global optimization; however, the -fast switch will vary from release to release depending on a reasonable selection of switches for any one particular release. The -O or -O2 level performs all level-one local optimizations as well as global optimizations. Control flow analysis is applied and global registers are allocated for all functions and subroutines. Loop regions are given special consideration. This optimization level is a good choice when the program contains loops, the loops are short, and the structure of the code is regular.

    The PGI compilers perform many different types of global optimizations, including but not limited to:

    • Branch to branch elimination
    • Constant propagation
    • Copy propagation
    • Dead store elimination
    • Global register allocation
    • Invariant code motion
    • Induction variable elimination
  • Includes:
    • -O1
• • -O1
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Level-one optimization specifies local optimization (-O1). The compiler performs scheduling of basic blocks as well as register allocation. This optimization level is a good choice when the code is very irregular; that is it contains many short statements containing IF statements and the program does not contain loops (DO or DO WHILE statements). For certain types of code, this optimization level may perform better than level-two (-O2) although this case rarely occurs.

    The PGI compilers perform many different types of local optimizations, including but not limited to:

    • Algebraic identity removal
    • Constant folding
    • Common subexpression elimination
    • Local register optimization
    • Peephole optimizations
    • Redundant load and store elimination
    • Strength reductions
    Note that this is the default optimiation level when no optimization flags are specified on the compilation command line.
• • -Munroll=c:1
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Instructs the compiler to completely unroll loops with a constant loop count of less than or equal to 1 where 1 is a supplied constant value. If no constant value is given, then a default of 4 is used. A value of 1 inhibits the complete unrolling of loops with constant loop counts.

  • Includes:
    • -Munroll
• • -Munroll
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Invokes the loop unroller.

• • -Mautoinline
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Inline functions declared with the inline keyword.

• • -Msmart
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Enable an optional post-pass instruction scheduling.

• • -Mlre
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Enables loop-carried redundancy elimination, an optimization that can reduce the number of arithmetic operations and memory references in loops.

• • -Mnoframe
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Eliminates operations that set up a true stack frame pointer for every function. With this option enabled, you cannot perform a traceback on the generated code and you cannot access local variables.

• • -Mvect=sse
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Instructs the vectorizer to search for vectorizable loops and, where possible, make use of SSE, SSE2, and prefetch instructions.

  • Includes:
    • -Mvect
      • -Mvect=assoc
      • -Mvect=altcode
• • -Mvect
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Enable automatic vector pipelining.

  • Includes:
    • -Mvect=assoc
    • -Mvect=altcode
• • -Mvect=assoc
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Instructs the vectorizer to enable certain associativity conversions that can change the results of a computations due to roundoff error. A typical optimization is to change an arithmetic operation to an arithmetic opteration that is mathmatically correct, but can be computationally different, due to round-off error.

• • -Mvect=altcode
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Instructs the vectorizer to generate alternate code for vectorized loops when appropriate. For each vectorized loop the compiler decides whether to generate altcode and what type or types to generate, which may be any or all of:

    • Altcode without iteration peeling
    • Altcode with non-temporal stores and other data cache optimizations
    • Altcode base on array alignments calculated dynamically at runtime.

    The compiler also determines suitable loop count and array alignment conditions for executing the altcode.

• • -Mcache_align
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Align "unconstrained" data objects of size greater than or equal to 16 bytes on cache-line boundaries. An "unconstrained" object is a variable or array that is not a member of an aggregate structure or common block, is not allocatable, and is not an automatic array. On by default on 64-bit Linux systems.

• • -Mflushz
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Set SSE to flush-to-zero mode; if a floating-point underflow occurs, the value is set to zero.

• • -Mdaz
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Treat denormalized numbers as zero. Included with "-fast" on Intel based systems. For AMD based systems, "-Mdaz" is not included by default with "-fast".

• • -Mscalarsse
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Use SSE/SSE2 instructions to perform scalar floating-point arithmetic on targets where these instructions are supported. This option is default on SSE2 enabled target architectures.

• • -Mfprelaxed=rsqrt
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Instructs the compiler to use relaxed precision in the calculation of floating-point reciprocal square root (1/sqrt). Can result in improved performance at the expense of numerical accuracy.

• • -Mfprelaxed=sqrt
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Instructs the compiler to use relaxed precision in the calculation of floating-point square root. Can result in improved performance at the expense of numerical accuracy.

• • -Mfprelaxed=div
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Instructs the compiler to use relaxed precision in the calculation of floating-point division. Can result in improved performance at the expense of numerical accuracy.

• • -Mfprelaxed=order
  • 
  • pgcc_l, pgcpp_l, pgcplusplus_l, pgf95_l, pgfortran_l, pgcc_w, pgcpp_w, pgf95_w, pgfortran_w

  • Instructs the compiler to allow floating-point expression reordering, including factoring. Can result in improved performance at the expense of numerical accuracy.

Shell, Environment, and Other Software Settings

AMD BIOS settings

maximizes performance and minimizes latency with little regard to power consumption

Can be used to disable symmetric multithreading. To re-enable SMT, a POWER CYCLE is needed after selecting the 'Auto' option. WARNING - S3 is NOT SUPPORTED on systems where SMT is disabled.

Specifies the number of desired NUMA nodes per socket. Zero will attempt to interleave the two sockets together.

Machine Configurations

BIOS settings

Maximum Performance

Mode will maximize the absolute performance of the system without regard for power. In this mode, power consumption is a don't care. Things like fan speed and heat output of the system may increase in addition to power consumption. Efficiency of the system may go down in this mode, but the absolute performance may increase depending on the workload that is running.

Custom

Allows the user to individually modify any of the low-level settings that are preset and unchangeable in any of the other 4 preset modes.

Hyper-Threading

Enabling Hyper-Threading let operating system addresses two virtual or logical cores for a physical presented core. Workloads can be shared between virtual or logical cores when possible. The main function of hyper-threading is to increase the number of independent instructions in the pipeline for using the processor resources more efficiently.

C-States

Legacy: When "Legacy" is selected, the operating system initiates the C-state transitions. For E5/E7 CPUs, ACPI C1/C2/C3 map to Intel C1/C3/C6. For 6500/7500 CPUs, ACPI C1/C3 map to Intel C1/C3 (ACPI C2 is not available). Some OS SW may defeat the ACPI mapping (e.g. intel_idle driver). Autonomous: When "Autonomous" is selected, HALT and C1 request get converted to C6 requests in hardware. Disable: When "Disable" is selected, only C0 and C1 are used by the OS. C1 gets enabled automatically when an OS autohalts.

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Flag description origin markings:

	Indicates that the flag description came from the user flags file.
	Indicates that the flag description came from the suite-wide flags file.
	Indicates that the flag description came from a per-benchmark flags file.

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The flags files that were used to format this result can be browsed at
https://www.spec.org/accel/flags/pgi2014_flags.20190321.html,
https://www.spec.org/accel/flags/Lenovo-SPECACCEL1.2_Platform_Flags.20190807.html.

You can also download the XML flags sources by saving the following links:
https://www.spec.org/accel/flags/pgi2014_flags.20190321.xml,
https://www.spec.org/accel/flags/Lenovo-SPECACCEL1.2_Platform_Flags.20190807.xml.

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For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2015-2019 Standard Performance Evaluation Corporation
Tested with SPEC ACCEL v1.2.
Report generated on Wed Aug 7 19:04:33 2019 by SPEC ACCEL flags formatter v1290.