Base Compiler Invocation
C benchmarks
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- gcc
![[user]](http://www.spec.org/auto/accel/flags/user.png)
- CC, LD
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Invoke the GNU C compiler
Fortran benchmarks
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- gfortran
- FC, LD
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Invoke the GNU Fortran compiler
Invoke the GNU C compiler
Invoke the GNU Fortran compiler
![[benchmark]](http://www.spec.org/auto/accel/flags/benchmark.png)
Used in lbm.c if you must have the explicit size listed rather than use implicit size.
Disregard strict standards compliance. -Ofast enables all -O3 optimizations. It also enables optimizations that are not valid for all standard-compliant programs. It turns on -ffast-math and the Fortran-specific -fno-protect-parens and -fstack-arrays.
Enable handling of OpenMP directives "#pragma omp" in C/C++ and
"!$omp" in Fortran. When -fopenmp is specified, the compiler
generates parallel code according to the OpenMP Application
Program Interface v4.0
Enable handling of OpenMP's SIMD directives with "#pragma omp" in C/C++ and "!$omp" in Fortran. Other OpenMP directives are ignored.
Generate code for 32-bit or 64-bit ABI.
Intel AVX-512 Foundation instructions (AVX-512F) are the base of Intel AVX-512. They include extensions of the Intel AVX and Intel AVX2 family of SIMD instructions but are encoded using EVEX encoding scheme with support for 512-bit vector registers, up to 32 vector registers in 64-bit mode, and conditional processing using opmask registers.
Intel AVX-512 Conflict Detection instructions (AVX-512CD) provide efficient conflict detection to allow more loops to be vectorized.
Intel AVX-512 Exponential and Reciprocal instructions (AVX-512ER) are designed to provide building blocks for accelerating certain transcendental math computations.
Intel AVX-512 Prefetch instructions (AVX-512PF) are new instructions that can be useful for reducing memory operation latency exposure that involve gather/scatter instructions.
Disregard strict standards compliance. -Ofast enables all -O3 optimizations. It also enables optimizations that are not valid for all standard-compliant programs. It turns on -ffast-math and the Fortran-specific -fno-protect-parens and -fstack-arrays.
Enable handling of OpenMP directives "#pragma omp" in C/C++ and
"!$omp" in Fortran. When -fopenmp is specified, the compiler
generates parallel code according to the OpenMP Application
Program Interface v4.0
Enable handling of OpenMP's SIMD directives with "#pragma omp" in C/C++ and "!$omp" in Fortran. Other OpenMP directives are ignored.
Generate code for 32-bit or 64-bit ABI.
Intel AVX-512 Foundation instructions (AVX-512F) are the base of Intel AVX-512. They include extensions of the Intel AVX and Intel AVX2 family of SIMD instructions but are encoded using EVEX encoding scheme with support for 512-bit vector registers, up to 32 vector registers in 64-bit mode, and conditional processing using opmask registers.
Intel AVX-512 Conflict Detection instructions (AVX-512CD) provide efficient conflict detection to allow more loops to be vectorized.
Intel AVX-512 Exponential and Reciprocal instructions (AVX-512ER) are designed to provide building blocks for accelerating certain transcendental math computations.
Intel AVX-512 Prefetch instructions (AVX-512PF) are new instructions that can be useful for reducing memory operation latency exposure that involve gather/scatter instructions.
Disregard strict standards compliance. -Ofast enables all -O3 optimizations. It also enables optimizations that are not valid for all standard-compliant programs. It turns on -ffast-math and the Fortran-specific -fno-protect-parens and -fstack-arrays.
Enable handling of OpenMP directives "#pragma omp" in C/C++ and
"!$omp" in Fortran. When -fopenmp is specified, the compiler
generates parallel code according to the OpenMP Application
Program Interface v4.0
Enable handling of OpenMP's SIMD directives with "#pragma omp" in C/C++ and "!$omp" in Fortran. Other OpenMP directives are ignored.
Generate code for 32-bit or 64-bit ABI.
Intel AVX-512 Foundation instructions (AVX-512F) are the base of Intel AVX-512. They include extensions of the Intel AVX and Intel AVX2 family of SIMD instructions but are encoded using EVEX encoding scheme with support for 512-bit vector registers, up to 32 vector registers in 64-bit mode, and conditional processing using opmask registers.
Intel AVX-512 Conflict Detection instructions (AVX-512CD) provide efficient conflict detection to allow more loops to be vectorized.
Intel AVX-512 Exponential and Reciprocal instructions (AVX-512ER) are designed to provide building blocks for accelerating certain transcendental math computations.
Intel AVX-512 Prefetch instructions (AVX-512PF) are new instructions that can be useful for reducing memory operation latency exposure that involve gather/scatter instructions.
Control NUMA policy for processes or shared memory.
--membind=nodes, -m nodes
Only allocate memory from nodes. Allocation will fail when there is not enough memory available on these nodes. Nodes may be specified as noted above
--preferred=node, -p node
Preferably allocate memory on node, but if memory cannot be allocated then fall back to other nodes. This option takes only a single node number. Relative notation may be used.
Flag description origin markings:
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Indicates that the flag description came from the user flags file. |
![[suite]](http://www.spec.org/auto/accel/flags/suite.png) |
Indicates that the flag description came from the suite-wide flags file. |
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Indicates that the flag description came from a per-benchmark flags file. |
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2015-2017 Standard Performance Evaluation Corporation
Tested with SPEC ACCEL v75.
Report generated on Wed Jun 21 17:14:59 2017 by SPEC ACCEL flags formatter v1290.