SPEC OMPL2001 Summary Hewlett-Packard Company HP Integrity Superdome 64-way (1500 MHz Itanium 2) Sat Dec 6 13:40:02 2003 SPEC License #HPG2116 Tester: Hewlett-Packard Company Test date: Dec-2003 Test Site: Richardson, Texas Hardware availability: Oct-2003 Software availability: Jan-2004 Base Base Base Peak Peak Peak Benchmarks Ref Time Run Time Ratio Ref Time Run Time Ratio ------------- -------- -------- -------- -------- -------- -------- 311.wupwise_l 9200 358 411437* 9200 358 411437* 311.wupwise_l 9200 350 420093 9200 350 420093 313.swim_l 12500 468 427116 12500 468 427116 313.swim_l 12500 470 425590* 12500 470 425590* 315.mgrid_l 13500 849 254473 13500 849 254473 315.mgrid_l 13500 953 226699* 13500 953 226699* 317.applu_l 13500 585 369069* 13500 541 398926* 317.applu_l 13500 574 376514 13500 535 403779 321.equake_l 13000 2738 75965* 13000 2738 75965* 321.equake_l 13000 2702 76978 13000 2702 76978 325.apsi_l 10500 608 276335 10500 461 364508* 325.apsi_l 10500 616 272725* 10500 460 365170 327.gafort_l 11000 618 284664* 11000 618 284664* 327.gafort_l 11000 617 285132 11000 617 285132 329.fma3d_l 23500 1294 290562* 23500 1294 290562* 329.fma3d_l 23500 1286 292364 23500 1286 292364 331.art_l 25000 693 577463 25000 670 596969 331.art_l 25000 693 577270* 25000 671 596390* ======================================================================== 311.wupwise_l 9200 358 411437* 9200 358 411437* 313.swim_l 12500 470 425590* 12500 470 425590* 315.mgrid_l 13500 953 226699* 13500 953 226699* 317.applu_l 13500 585 369069* 13500 541 398926* 321.equake_l 13000 2738 75965* 13000 2738 75965* 325.apsi_l 10500 616 272725* 10500 461 364508* 327.gafort_l 11000 618 284664* 11000 618 284664* 329.fma3d_l 23500 1294 290562* 23500 1294 290562* 331.art_l 25000 693 577270* 25000 671 596390* SPECompLbase2001 289967 SPECompLpeak2001 303161 HARDWARE -------- Hardware Vendor: Hewlett-Packard Company Model Name: HP Integrity Superdome 64-way (1500 MHz Itanium 2) CPU: Intel Itanium 2 CPU MHz: 1500 FPU: Integrated CPU(s) enabled: 64 CPU(s) orderable: 6 to 64 by 2 Primary Cache: L1 Inst/Data: 16 KB, associativity = 4 Secondary Cache: L2 Unified: 256 KB, associativity = 8 L3 Cache: L3 Unified: 6144 KB, associativity = 24 Other Cache: None Memory: 256GB (512 * 512MB DIMMs) Disk Subsystem: root disk 1x36 SCSI 9x36GB Fibrechannel (striped) Other Hardware: -- SOFTWARE -------- OpenMP Threads: 64 Parallel: OpenMP Operating System: HPUX11i-TCOE B.11.23 Compiler: HP C/ANSI C Compiler C.05.55 HP aC++ Compiler C.05.55 HP Fortran 90 Compiler B.11.23.03 HP LIBF90 PHSS_29620 HP F90 Compiler PHSS_29663 HPUX OS Patch PHKL_30089 File System: vxfs System State: Multi-user NOTES ----- User environment: MP_IDLE_THREADS_WAIT=-1 OMP_FIRST_USE=0 Base: F90 +Ofaster +DSitanium2 +Oopenmp +Oinfo +DD64 -minshared cc +Ofaster +Oopenmp +DD64 +Oinfo +DSitanium2 -minshared -AOe +Ofltacc=default submit = chatr -s +id disable +pd 64k +pi 64k $commandexe; \ _M_ARENA_OPTS=64:32 _M_SBA_OPTS=16348:150:256 \ mpsched -T FILL $command Peak: 311.wupwise_l: basepeak=true 313.swim_l: basepeak=true 315.mgrid_l: basepeak=true 317.applu_l: +Ofaster +DSitanium2 +Oopenmp +Oinfo +DD64 -minshared ONESTEP=true submit = chatr -s +id enable $commandexe; _M_ARENA_OPTS=64:32 mpsched -T FILL $command 321.equake_l: basepeak=true 325.apsi_l: +Ofaster +DSitanium2 +Oopenmp +Oinfo +DD64 -minshared submit = chatr -s +id disable +pd 256k +pi 256k $commandexe; _ M_ARENA_OPTS=64:32 mpsched -T FILL $command 327.gafort_l: basepeak=true 329.fma3d_l: basepeak=true 331.art_l: +Ofaster +Oopenmp +DD64 +Oinfo +DSitanium2 -minshared -AOe +Ofltacc=default submit = chatr -s +id disable +pd 256k +pi 256k $commandexe; _M_ARENA_OPTS=64:32 _M_SBA_OPTS=16348:150:256 mpsched -T FILL $command Alternate Sources: None Kernel Paramters (/stand/system): maxdsiz 0xc0000000 maxdsiz_64bit 0x3ffbfffffff maxssiz 0x17f00000 maxssiz_64bit 0x40000000 maxtsiz 0x40000000 maxtsiz_64bit 0x40000000 vps_pagesize 4096 vps_ceiling 16384 dbc_min_pct 20 dbc_max_pct 20 swapmem_on 0 Notes: System was configured with 1/2 of memory interleaved and 1/2 of memory local to each cell System configured as a single partiton with 16 cells and 4 processors per cell Threads were assigned to cpus using the FILL strategy from the HP-UX mpsched utility Memory tuning is documented in man page malloc(3C) _M_ARENA_OPTS=64:32 64 malloc arenas, 32 4k pages expansion _M_SBA_OPTS=16348:150:256 16384 maxfast size, 150 small blocks, 256 grain size ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 1999-2002 Standard Performance Evaluation Corporation Generated on Wed Dec 24 12:09:52 2003 by SPEC OMP2001 ASCII formatter v2.1