MPI2007 Flag Description
Colfax International Intel Xeon Phi 7210, 1.30 GHz, SMT on, Turbo off, flat (MCDRAM preferred)
Test sponsored by Indiana University
Copyright © 2016 Intel Corporation. All Rights Reserved.
Base Optimization Flags
-
- -O3
![[user]](http://www.spec.org/auto/mpi2007/flags/user.png)
- OPTIMIZE
-
Enables O2 optimizations plus more aggressive optimizations,
such as prefetching, scalar replacement, and loop and memory
access transformations. Enables optimizations for maximum speed,
such as:
- Loop unrolling, including instruction scheduling
- Code replication to eliminate branches
- Padding the size of certain power-of-two arrays to allow
more efficient cache use.
On IA-32 and Intel EM64T processors, when O3 is used with options
-ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler
performs more aggressive data dependency analysis than for O2, which
may result in longer compilation times.
The O3 optimizations may not cause higher performance unless loop and
memory access transformations take place. The optimizations may slow
down code in some cases compared to O2 optimizations.
The O3 option is recommended for applications that have loops that heavily
use floating-point calculations and process large data sets. On IA-32
Windows platforms, -O3 sets the following:
/GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2
- Includes:
-
- -xMIC-AVX512
- OPTIMIZE
-
May generate Intel(R) Advanced Vector Extensions 512
(Intel(R) AVX-512) Foundation instructions, Intel(R) AVX-512
Conflict Detection instructions, Intel(R) AVX-512 Exponential
and Reciprocal instructions, Intel(R) AVX-512 Prefetch
instructions for Intel(R) processors, and the instructions
enabled with CORE-AVX2.
-
- -no-prec-div
- OPTIMIZE
-
(disable/enable[default] -[no-]prec-div)
-prec-div improves precision of floating-point divides. It has a slight
impact on speed. -no-prec-div disables this option and enables
optimizations that give slightly less precise results than full IEEE
division.
When you specify -no-prec-div along with some optimizations, such as
-xN and -xB (Linux) or /QxN and /QxB (Windows),
the compiler may change floating-point division computations into multiplication
by the reciprocal of the denominator.
For example, A/B is computed as A * (1/B) to improve the speed of the
computation.
However, sometimes the value produced by this transformation is
not as accurate as full IEEE division. When it is important to have fully
precise IEEE division, do not use -no-prec-div which will enable the
default -prec-div and the result is more accurate, with some
loss of performance.
-
- -fp-model fast=2
- OPTIMIZE
-
enable floating point model variation
[no-]except - enable/disable floating point semantics
fast[=1|2] - enables more aggressive floating point optimizations
precise - allows value-safe optimizations
source - enables intermediates in source precision
strict - enables -fp-model precise -fp-model except, disables
contractions and enables pragma stdc fenv_access
double - rounds intermediates in 53-bit (double) precision
extended - rounds intermediates in 64-bit (extended) precision
-
-
-
- -O3
- OPTIMIZE
-
Enables O2 optimizations plus more aggressive optimizations,
such as prefetching, scalar replacement, and loop and memory
access transformations. Enables optimizations for maximum speed,
such as:
- Loop unrolling, including instruction scheduling
- Code replication to eliminate branches
- Padding the size of certain power-of-two arrays to allow
more efficient cache use.
On IA-32 and Intel EM64T processors, when O3 is used with options
-ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler
performs more aggressive data dependency analysis than for O2, which
may result in longer compilation times.
The O3 optimizations may not cause higher performance unless loop and
memory access transformations take place. The optimizations may slow
down code in some cases compared to O2 optimizations.
The O3 option is recommended for applications that have loops that heavily
use floating-point calculations and process large data sets. On IA-32
Windows platforms, -O3 sets the following:
/GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2
- Includes:
-
- -xMIC-AVX512
- OPTIMIZE
-
May generate Intel(R) Advanced Vector Extensions 512
(Intel(R) AVX-512) Foundation instructions, Intel(R) AVX-512
Conflict Detection instructions, Intel(R) AVX-512 Exponential
and Reciprocal instructions, Intel(R) AVX-512 Prefetch
instructions for Intel(R) processors, and the instructions
enabled with CORE-AVX2.
-
- -no-prec-div
- OPTIMIZE
-
(disable/enable[default] -[no-]prec-div)
-prec-div improves precision of floating-point divides. It has a slight
impact on speed. -no-prec-div disables this option and enables
optimizations that give slightly less precise results than full IEEE
division.
When you specify -no-prec-div along with some optimizations, such as
-xN and -xB (Linux) or /QxN and /QxB (Windows),
the compiler may change floating-point division computations into multiplication
by the reciprocal of the denominator.
For example, A/B is computed as A * (1/B) to improve the speed of the
computation.
However, sometimes the value produced by this transformation is
not as accurate as full IEEE division. When it is important to have fully
precise IEEE division, do not use -no-prec-div which will enable the
default -prec-div and the result is more accurate, with some
loss of performance.
-
- -fp-model fast=2
- OPTIMIZE
-
enable floating point model variation
[no-]except - enable/disable floating point semantics
fast[=1|2] - enables more aggressive floating point optimizations
precise - allows value-safe optimizations
source - enables intermediates in source precision
strict - enables -fp-model precise -fp-model except, disables
contractions and enables pragma stdc fenv_access
double - rounds intermediates in 53-bit (double) precision
extended - rounds intermediates in 64-bit (extended) precision
-
-
-
- -O3
- OPTIMIZE
-
Enables O2 optimizations plus more aggressive optimizations,
such as prefetching, scalar replacement, and loop and memory
access transformations. Enables optimizations for maximum speed,
such as:
- Loop unrolling, including instruction scheduling
- Code replication to eliminate branches
- Padding the size of certain power-of-two arrays to allow
more efficient cache use.
On IA-32 and Intel EM64T processors, when O3 is used with options
-ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler
performs more aggressive data dependency analysis than for O2, which
may result in longer compilation times.
The O3 optimizations may not cause higher performance unless loop and
memory access transformations take place. The optimizations may slow
down code in some cases compared to O2 optimizations.
The O3 option is recommended for applications that have loops that heavily
use floating-point calculations and process large data sets. On IA-32
Windows platforms, -O3 sets the following:
/GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2
- Includes:
-
- -xMIC-AVX512
- OPTIMIZE
-
May generate Intel(R) Advanced Vector Extensions 512
(Intel(R) AVX-512) Foundation instructions, Intel(R) AVX-512
Conflict Detection instructions, Intel(R) AVX-512 Exponential
and Reciprocal instructions, Intel(R) AVX-512 Prefetch
instructions for Intel(R) processors, and the instructions
enabled with CORE-AVX2.
-
- -no-prec-div
- OPTIMIZE
-
(disable/enable[default] -[no-]prec-div)
-prec-div improves precision of floating-point divides. It has a slight
impact on speed. -no-prec-div disables this option and enables
optimizations that give slightly less precise results than full IEEE
division.
When you specify -no-prec-div along with some optimizations, such as
-xN and -xB (Linux) or /QxN and /QxB (Windows),
the compiler may change floating-point division computations into multiplication
by the reciprocal of the denominator.
For example, A/B is computed as A * (1/B) to improve the speed of the
computation.
However, sometimes the value produced by this transformation is
not as accurate as full IEEE division. When it is important to have fully
precise IEEE division, do not use -no-prec-div which will enable the
default -prec-div and the result is more accurate, with some
loss of performance.
-
- -fp-model fast=2
- OPTIMIZE
-
enable floating point model variation
[no-]except - enable/disable floating point semantics
fast[=1|2] - enables more aggressive floating point optimizations
precise - allows value-safe optimizations
source - enables intermediates in source precision
strict - enables -fp-model precise -fp-model except, disables
contractions and enables pragma stdc fenv_access
double - rounds intermediates in 53-bit (double) precision
extended - rounds intermediates in 64-bit (extended) precision
-
-
-
- -O3
- OPTIMIZE
-
Enables O2 optimizations plus more aggressive optimizations,
such as prefetching, scalar replacement, and loop and memory
access transformations. Enables optimizations for maximum speed,
such as:
- Loop unrolling, including instruction scheduling
- Code replication to eliminate branches
- Padding the size of certain power-of-two arrays to allow
more efficient cache use.
On IA-32 and Intel EM64T processors, when O3 is used with options
-ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler
performs more aggressive data dependency analysis than for O2, which
may result in longer compilation times.
The O3 optimizations may not cause higher performance unless loop and
memory access transformations take place. The optimizations may slow
down code in some cases compared to O2 optimizations.
The O3 option is recommended for applications that have loops that heavily
use floating-point calculations and process large data sets. On IA-32
Windows platforms, -O3 sets the following:
/GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2
- Includes:
-
- -xMIC-AVX512
- OPTIMIZE
-
May generate Intel(R) Advanced Vector Extensions 512
(Intel(R) AVX-512) Foundation instructions, Intel(R) AVX-512
Conflict Detection instructions, Intel(R) AVX-512 Exponential
and Reciprocal instructions, Intel(R) AVX-512 Prefetch
instructions for Intel(R) processors, and the instructions
enabled with CORE-AVX2.
-
- -no-prec-div
- OPTIMIZE
-
(disable/enable[default] -[no-]prec-div)
-prec-div improves precision of floating-point divides. It has a slight
impact on speed. -no-prec-div disables this option and enables
optimizations that give slightly less precise results than full IEEE
division.
When you specify -no-prec-div along with some optimizations, such as
-xN and -xB (Linux) or /QxN and /QxB (Windows),
the compiler may change floating-point division computations into multiplication
by the reciprocal of the denominator.
For example, A/B is computed as A * (1/B) to improve the speed of the
computation.
However, sometimes the value produced by this transformation is
not as accurate as full IEEE division. When it is important to have fully
precise IEEE division, do not use -no-prec-div which will enable the
default -prec-div and the result is more accurate, with some
loss of performance.
-
- -fp-model fast=2
- OPTIMIZE
-
enable floating point model variation
[no-]except - enable/disable floating point semantics
fast[=1|2] - enables more aggressive floating point optimizations
precise - allows value-safe optimizations
source - enables intermediates in source precision
strict - enables -fp-model precise -fp-model except, disables
contractions and enables pragma stdc fenv_access
double - rounds intermediates in 53-bit (double) precision
extended - rounds intermediates in 64-bit (extended) precision
-
-
Implicitly Included Flags
This section contains descriptions of flags that were included implicitly
by other flags, but which do not have a permanent home at SPEC.
-
-
-
- -Ob_n
-
Specifies the level of inline function expansion.
Ob0 - Disables inlining of user-defined functions. Note that
statement functions are always inlined.
Ob1 - Enables inlining when an inline keyword or an inline
attribute is specified. Also enables inlining according
to the C++ language.
Ob2 - Enables inlining of any function at the compiler's
discretion.
-
- -O2
-
Enables optimizations for speed. This is the generally recommended
optimization level. This option also enables:
- Inlining of intrinsics
- Intra-file interprocedural optimizations, which include:
- inlining
- constant propagation
- forward substitution
- routine attribute propagation
- variable address-taken analysis
- dead static function elimination
- removal of unreferenced variables
- The following capabilities for performance gain:
- constant propagation
- copy propagation
- dead-code elimination
- global register allocation
- global instruction scheduling and control speculation
- loop unrolling
- optimized code selection
- partial redundancy elimination
- strength reduction/induction variable simplification
- variable renaming
- exception handling optimizations
- tail recursions
- peephole optimizations
- structure assignment lowering and optimizations
- dead store elimination
On IA-32 Windows platforms, -O2 sets the following:
/Og, /Oi-, /Os, /Oy, /Ob2, /GF (/Qvc7 and above), /Gf (/Qvc6
and below), /Gs, and /Gy.
- Includes:
-
-
-
-
-
-
-
- -O1
-
Enables optimizations for speed and disables some optimizations that
increase code size and affect speed.
To limit code size, this option:
- Enables global optimization; this includes data-flow analysis,
code motion, strength reduction and test replacement, split-lifetime
analysis, and instruction scheduling.
- Disables intrinsic recognition and intrinsics inlining.
The O1 option may improve performance for applications with very large
code size, many branches, and execution time not dominated by code within loops.
On IA-32 Windows platforms, -O1 sets the following:
/Qunroll0, /Oi-, /Op-, /Oy, /Gy, /Os, /GF (/Qvc7 and above),
/Gf (/Qvc6 and below), /Ob2, and /Og
- Includes:
-
-
This result has been formatted using multiple flags files.
The "platform settings" from each of them appears next.
Platform settings from EM64T_Intel_flags
SPEC MPI2007 Flag Description for the Intel(R) C++ Compiler 16.0
for IA32 and Intel 64 applications and Intel(R) Fortran Compiler 16.0 for IA32 and Intel 64
applications
Intel(R) MPI Library 4.1.1 for Linux* options and environment variables
Job startup command flags
-n <# of processes> or -np <# of processes>
Use this option to set the number of MPI processes to run the current arg-set.
-perhost <# of processes>
Use this option to place the indicated number of consecutive
MPI processes on every host in group round robin fashion. The number
of processes to start is controlled by the option -n as usual.
--parallel-startup
Use this option to allow parallel fast starting of mpd daemons under one local root.
No daemon checking is performed.
-genv <ENVVAR> <value>
Use this option to set the <ENVVAR> environment variable
to the specified <value> for all MPI processes.
Environment variables
I_MPI_DEVICE=<device>[:<provider>]
Select the particular network fabric to be used.
sock - Sockets
shm - Shared-memory only (no sockets)
ssm - Combined sockets + shared memory
(for clusters with SMP nodes)
rdma - RDMA-capable network fabrics including InfiniBand*,
Myrinet* (via DAPL*)
rdssm - Combined sockets + shared memory + DAPL*
(for clusters with SMP nodes and RDMA-capable network fabrics)
I_MPI_FALLBACK_DEVICE=(enable|disable)
Set this environment variable to enable fallback to the available
fabric. It is valid only for rdssm and rdma modes.
Fall back to the shared memory and/or socket fabrics
if initialization of the DAPL* fabric fails.
This is the default value.
Terminate the job if the fabric selected by the I_MPI_DEVICE
environment variable cannot be initialized.
Platform settings from colfax-knl
SPEC Flag Description for Intel Xeon Phi BIOS Setup and Tuning
Machine Configurations
BIOS settings
Simultaneous Multithreading
On 2nd generation Intel Xeon Phi processor and co-processors,
Simultaneous Multithreading (SMT),
permits 4 independent threads of execution on each core.
Cluster Mode:
This BIOS switch allows 5 options "All2All", "SNC-2", "SNC-4", "Hemisphere"
and "Quadrant". Quadrant mode divides the chip into 4 virtual Quadrants.
Quadrant mode can shorten the route length to memory,
and that enable us to enlarge the bandwidth of memory.
Memory Mode
This BIOS switch allows 3 options "Cache", "Flat", and "Hybrid".
Flat mode: the 16GB high bandwidth on-chip MCDRAM
shares a single contiguous address space as the DRAM and is
partitioned onto the second NUMA node.
Cache mode: the MCDRAMs is used as the cache of DDR memory.
Hybrid mode: a portion of the MCDRAM is used in flat mode, the rest is used as cache.
Turbo Mode
Enabling this switch allows the processor to provide more computing performance
at short notice by increasing the frequency above nominal frequency.
Other Tuning Information
numactl [ --preferred node ] [ --membind nodes ]
Control NUMA policy for processes or shared memory.
--membind=nodes, -m nodes
Only allocate memory from nodes. Allocation will fail when there is not enough memory available on
these nodes. Nodes may be specified as noted above
--preferred=node, -p node
Preferably allocate memory on node, but if memory cannot be allocated
then fall back to other nodes. This option takes only a single node number.
Relative notation may be used.
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2006-2010 Standard Performance Evaluation Corporation
Tested with SPEC MPI2007 v2.0.1.
Report generated on Wed Jan 11 12:44:21 2017 by SPEC MPI2007 flags formatter v1445.
![[benchmark]](http://www.spec.org/auto/mpi2007/flags/benchmark.png)
![[suite]](http://www.spec.org/auto/mpi2007/flags/suite.png)