MPI2007 Flag Description
QLogic, Intel, Supermicro QDR Benchmark Cluster (QLogic TrueScale InfiniBand, Intel Xeon X5570, 2.93 GHz)
Test sponsored by QLogic Corporation
Copyright © 2006 Intel Corporation. All Rights Reserved.
Base Optimization Flags
-
- -O3
![[user]](http://www.spec.org/auto/mpi2007/flags/user.png)
- COPTIMIZE
-
Enables O2 optimizations plus more aggressive optimizations,
such as prefetching, scalar replacement, and loop and memory
access transformations. Enables optimizations for maximum speed,
such as:
- Loop unrolling, including instruction scheduling
- Code replication to eliminate branches
- Padding the size of certain power-of-two arrays to allow
more efficient cache use.
On IA-32 and Intel EM64T processors, when O3 is used with options
-ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler
performs more aggressive data dependency analysis than for O2, which
may result in longer compilation times.
The O3 optimizations may not cause higher performance unless loop and
memory access transformations take place. The optimizations may slow
down code in some cases compared to O2 optimizations.
The O3 option is recommended for applications that have loops that heavily
use floating-point calculations and process large data sets. On IA-32
Windows platforms, -O3 sets the following:
/GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2
- Includes:
-
- -xSSE4.2
- COPTIMIZE
-
generate Intel(R) SSE4 Efficient Accelerated String and Text Processing
instructions supported by Intel(R) Core(TM) i7 processors. Can generate
Intel(R) SSE4 Vectorizing Compiler and Media Accelerator, Intel(R)
SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for the
Intel(R) Core(TM) processor family.
-
- -no-prec-div
- COPTIMIZE
-
(disable/enable[default] -Qprec-div[-])
-Qprec-div improves precision of floating-point divides. It has a slight
impact on speed. -Qprec-div- disables this option and enables
optimizations that give slightly less precise results than full IEEE
division.
When you specify -Qprec-div- along with some optimizations, such as
-xN and -xB (Linux) or /QxN and /QxB (Windows),
the compiler may change floating-point division computations into multiplication
by the reciprocal of the denominator.
For example, A/B is computed as A * (1/B) to improve the speed of the
computation.
However, sometimes the value produced by this transformation is
not as accurate as full IEEE division. When it is important to have fully
precise IEEE division, do not use -Qprec-div- which will enable the
default -Qprec-div and the result is more accurate, with some
loss of performance.
-
- -O3
- CXXOPTIMIZE
-
Enables O2 optimizations plus more aggressive optimizations,
such as prefetching, scalar replacement, and loop and memory
access transformations. Enables optimizations for maximum speed,
such as:
- Loop unrolling, including instruction scheduling
- Code replication to eliminate branches
- Padding the size of certain power-of-two arrays to allow
more efficient cache use.
On IA-32 and Intel EM64T processors, when O3 is used with options
-ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler
performs more aggressive data dependency analysis than for O2, which
may result in longer compilation times.
The O3 optimizations may not cause higher performance unless loop and
memory access transformations take place. The optimizations may slow
down code in some cases compared to O2 optimizations.
The O3 option is recommended for applications that have loops that heavily
use floating-point calculations and process large data sets. On IA-32
Windows platforms, -O3 sets the following:
/GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2
- Includes:
-
- -xSSE4.2
- CXXOPTIMIZE
-
generate Intel(R) SSE4 Efficient Accelerated String and Text Processing
instructions supported by Intel(R) Core(TM) i7 processors. Can generate
Intel(R) SSE4 Vectorizing Compiler and Media Accelerator, Intel(R)
SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for the
Intel(R) Core(TM) processor family.
-
- -no-prec-div
- CXXOPTIMIZE
-
(disable/enable[default] -Qprec-div[-])
-Qprec-div improves precision of floating-point divides. It has a slight
impact on speed. -Qprec-div- disables this option and enables
optimizations that give slightly less precise results than full IEEE
division.
When you specify -Qprec-div- along with some optimizations, such as
-xN and -xB (Linux) or /QxN and /QxB (Windows),
the compiler may change floating-point division computations into multiplication
by the reciprocal of the denominator.
For example, A/B is computed as A * (1/B) to improve the speed of the
computation.
However, sometimes the value produced by this transformation is
not as accurate as full IEEE division. When it is important to have fully
precise IEEE division, do not use -Qprec-div- which will enable the
default -Qprec-div and the result is more accurate, with some
loss of performance.
-
- -O3
- FOPTIMIZE
-
Enables O2 optimizations plus more aggressive optimizations,
such as prefetching, scalar replacement, and loop and memory
access transformations. Enables optimizations for maximum speed,
such as:
- Loop unrolling, including instruction scheduling
- Code replication to eliminate branches
- Padding the size of certain power-of-two arrays to allow
more efficient cache use.
On IA-32 and Intel EM64T processors, when O3 is used with options
-ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler
performs more aggressive data dependency analysis than for O2, which
may result in longer compilation times.
The O3 optimizations may not cause higher performance unless loop and
memory access transformations take place. The optimizations may slow
down code in some cases compared to O2 optimizations.
The O3 option is recommended for applications that have loops that heavily
use floating-point calculations and process large data sets. On IA-32
Windows platforms, -O3 sets the following:
/GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2
- Includes:
-
- -xSSE4.2
- FOPTIMIZE
-
generate Intel(R) SSE4 Efficient Accelerated String and Text Processing
instructions supported by Intel(R) Core(TM) i7 processors. Can generate
Intel(R) SSE4 Vectorizing Compiler and Media Accelerator, Intel(R)
SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for the
Intel(R) Core(TM) processor family.
-
- -no-prec-div
- FOPTIMIZE
-
(disable/enable[default] -Qprec-div[-])
-Qprec-div improves precision of floating-point divides. It has a slight
impact on speed. -Qprec-div- disables this option and enables
optimizations that give slightly less precise results than full IEEE
division.
When you specify -Qprec-div- along with some optimizations, such as
-xN and -xB (Linux) or /QxN and /QxB (Windows),
the compiler may change floating-point division computations into multiplication
by the reciprocal of the denominator.
For example, A/B is computed as A * (1/B) to improve the speed of the
computation.
However, sometimes the value produced by this transformation is
not as accurate as full IEEE division. When it is important to have fully
precise IEEE division, do not use -Qprec-div- which will enable the
default -Qprec-div and the result is more accurate, with some
loss of performance.
-
- -O3
- COPTIMIZE, FOPTIMIZE
-
Enables O2 optimizations plus more aggressive optimizations,
such as prefetching, scalar replacement, and loop and memory
access transformations. Enables optimizations for maximum speed,
such as:
- Loop unrolling, including instruction scheduling
- Code replication to eliminate branches
- Padding the size of certain power-of-two arrays to allow
more efficient cache use.
On IA-32 and Intel EM64T processors, when O3 is used with options
-ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler
performs more aggressive data dependency analysis than for O2, which
may result in longer compilation times.
The O3 optimizations may not cause higher performance unless loop and
memory access transformations take place. The optimizations may slow
down code in some cases compared to O2 optimizations.
The O3 option is recommended for applications that have loops that heavily
use floating-point calculations and process large data sets. On IA-32
Windows platforms, -O3 sets the following:
/GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2
- Includes:
-
- -xSSE4.2
- COPTIMIZE, FOPTIMIZE
-
generate Intel(R) SSE4 Efficient Accelerated String and Text Processing
instructions supported by Intel(R) Core(TM) i7 processors. Can generate
Intel(R) SSE4 Vectorizing Compiler and Media Accelerator, Intel(R)
SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for the
Intel(R) Core(TM) processor family.
-
- -no-prec-div
- COPTIMIZE, FOPTIMIZE
-
(disable/enable[default] -Qprec-div[-])
-Qprec-div improves precision of floating-point divides. It has a slight
impact on speed. -Qprec-div- disables this option and enables
optimizations that give slightly less precise results than full IEEE
division.
When you specify -Qprec-div- along with some optimizations, such as
-xN and -xB (Linux) or /QxN and /QxB (Windows),
the compiler may change floating-point division computations into multiplication
by the reciprocal of the denominator.
For example, A/B is computed as A * (1/B) to improve the speed of the
computation.
However, sometimes the value produced by this transformation is
not as accurate as full IEEE division. When it is important to have fully
precise IEEE division, do not use -Qprec-div- which will enable the
default -Qprec-div and the result is more accurate, with some
loss of performance.
Implicitly Included Flags
This section contains descriptions of flags that were included implicitly
by other flags, but which do not have a permanent home at SPEC.
-
-
-
- -Ob_n
-
Specifies the level of inline function expansion.
Ob0 - Disables inlining of user-defined functions. Note that
statement functions are always inlined.
Ob1 - Enables inlining when an inline keyword or an inline
attribute is specified. Also enables inlining according
to the C++ language.
Ob2 - Enables inlining of any function at the compiler's
discretion.
-
- -O2
-
Enables optimizations for speed. This is the generally recommended
optimization level. This option also enables:
- Inlining of intrinsics
- Intra-file interprocedural optimizations, which include:
- inlining
- constant propagation
- forward substitution
- routine attribute propagation
- variable address-taken analysis
- dead static function elimination
- removal of unreferenced variables
- The following capabilities for performance gain:
- constant propagation
- copy propagation
- dead-code elimination
- global register allocation
- global instruction scheduling and control speculation
- loop unrolling
- optimized code selection
- partial redundancy elimination
- strength reduction/induction variable simplification
- variable renaming
- exception handling optimizations
- tail recursions
- peephole optimizations
- structure assignment lowering and optimizations
- dead store elimination
On IA-32 Windows platforms, -O2 sets the following:
/Og, /Oi-, /Os, /Oy, /Ob2, /GF (/Qvc7 and above), /Gf (/Qvc6
and below), /Gs, and /Gy.
- Includes:
-
-
-
-
-
-
-
- -O1
-
Enables optimizations for speed and disables some optimizations that
increase code size and affect speed.
To limit code size, this option:
- Enables global optimization; this includes data-flow analysis,
code motion, strength reduction and test replacement, split-lifetime
analysis, and instruction scheduling.
- Disables intrinsic recognition and intrinsics inlining.
The O1 option may improve performance for applications with very large
code size, many branches, and execution time not dominated by code within loops.
On IA-32 Windows platforms, -O1 sets the following:
/Qunroll0, /Oi-, /Op-, /Oy, /Gy, /Os, /GF (/Qvc7 and above),
/Gf (/Qvc6 and below), /Ob2, and /Og
- Includes:
-
-
Platform settings
One or more of the following settings may have been set. If so, the "General Notes" section of the
report will say so; and you can read below to find out more about what these settings mean.
Hardware Prefetch:
This BIOS option allows the enabling/disabling of a processor mechanism to
prefetch data into the cache according to a pattern-recognition algorithm.
In some cases, setting this option to Disabled may improve
performance. Users should only disable this option
after performing application benchmarking to verify improved
performance in their environment.
Adjacent Sector Prefetch:
This BIOS option allows the enabling/disabling of a processor mechanism to
fetch the adjacent cache line within an 128-byte sector that contains
the data needed due to a cache line miss.
In some cases, setting this option to Disabled may improve
performance. Users should only disable this option
after performing application benchmarking to verify improved
performance in their environment.
Snoop Filter Enabled/Disabled:
This BIOS option enables/disables the Snoop Filter. The Snoop Filter is designed to reduce system
bus utilization coming from cache misses. On the Intel 5000X and 5400 chipset, it is built as a
cache structure able to minimize unnecessary snoop traffic. When enabled, it can lead to
significant memory performance improvements for several workstation applications on suitable
memory configurations.
ulimit -s
Sets the stack size to n kbytes, or unlimited to allow the stack size
to grow without limit.
QLogic MPI Library v2.5 options and environment variables
The submit command shown below uses the QLogic MPI mpirun command to launch the MPI processes.
submit=
. $[I_ENV_HOME]/iccvars.sh intel64
. $[I_ENV_HOME]/ifortvars.sh intel64
mpirun -disable-mpi-progress-check -m %{hosts} -np $ranks $command
EOF
The SPEC config file feature
submit is used to launch MPI jobs. This specific submit command
used QLogic MPI's mpirun command to launch the jobs. Before launching the job,
variables are set appropriately for the QLogic MPI processes
and the Intel Compiler runtime libraries. Flags for the mpirun command are explained
below.
mpirun command flags
-disable-mpi-progress-check
Quiescence is a condition when no MPI messages are being sent or
received by ANY of the node processes, or there is a lack of
ping reply. QLogic MPI supports quiescence detection for
gracefully terminating buggy deadlocked programs.
This option disables MPI communication progress check without
disabling the ping reply check.
-np <# of processes>
Use this option to set the number of MPI processes to run the current arg-set.
-ppn <# of processes>
Use this option to place the indicated number of consecutive
MPI processes on every host in group round robin fashion. The number
of processes to start is controlled by the option -n as usual.
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2006-2010 Standard Performance Evaluation Corporation
Tested with SPEC MPI2007 v1.1.
Report generated on Tue Jul 22 13:38:21 2014 by SPEC MPI2007 flags formatter v1445.
![[benchmark]](http://www.spec.org/auto/mpi2007/flags/benchmark.png)
![[suite]](http://www.spec.org/auto/mpi2007/flags/suite.png)