CPU2017 Flag Description
Kaytus Systems Pte. Ltd. KR2280E2 (AMD EPYC 9174F)
Compilers: AMD Optimizing C/C++ Compiler Suite
Base Compiler Invocation
-
- clang
![[user]](https://www.spec.org/auto/cpu2017/images/user.png)
- CC, LD
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang++
- CXX, LD
-
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- flang
- FC, LD
-
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on
which high-level mode setting is passed, Flang will stop before doing a full link.
Peak Compiler Invocation
-
- clang
- CC, LD
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang++
- CXX, LD
-
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- flang
- FC, LD
-
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on
which high-level mode setting is passed, Flang will stop before doing a full link.
Base Portability Flags
-
![[suite]](https://www.spec.org/auto/cpu2017/images/suite.png)
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
Peak Portability Flags
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
Base Optimization Flags
-
- -m64
- CC, LD
-
Generates code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
- -O3
- COPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver4
- COPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products. -march=znver4 enables AVX 512 ISA for Genoa (znver4) processors.
-
-
- -ffast-math
- COPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -fstruct-layout=7
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled, if dead or redundant fields can be deleted, and if
the pointer or integer fields in the structure can be compressed. If feasible, this optimization transforms the code to
enable these improvements. This transformation is likely to improve cache utilization and memory bandwidth. It is expected
to improve the scalability of programs executed on multiple cores.
This is effective only under flto as the whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application; with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=0: disables structure peeling (default).
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of 64-bit integer type to 32-bit integer type. This is performed under a
strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of 64-bit integer type to 32-bit integer type. This is performed under a strict safety
check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit integer type to 16-bit integer type. This is performed under a strict
safety check.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit integer type to 16-bit integer type. This is performed under a strict
safety check.
- fstruct-layout=8: enables structure peeling, pointer compression, 64 bit integer type compression
as in level 6 and creates optimal ordering of peeled structure fields which could improve runtime performance.
- fstruct-layout=9: enables structure peeling, pointer compression, 64 bit integer type compression
as in level 7 and creates optimal ordering of peeled structure fields which could improve runtime performance.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of 64-bit integer fields to 32-bit integer fields in structures. Going from
fstruct-layout=4 to fstruct-layout=5 may result in higher performance if the pointer values are such that the pointers
can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstructlayout=3 respectively, with the
added feature of safe compression of 64 bit integer fields to 16 bit integer in structures. Going from fstruct-layout=6
to fstruct-layout=7 may result in higher performance if the pointer values are such that the pointers can be
compressed to 16-bits.
-
-
-
-
-
-
- -zopt
- COPTIMIZE
-
This option enables a subset of scalar, vector and loop transformations including improved variants of loop invariant code motion, SLP and loop vectorizations, loop-fusion, loop-interchange, loop-unswitch, loop tiling and loop distribution.
-
-
-
-
- -m64
- CXX, LD
-
Generates code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
- -O3
- CXXOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver4
- CXXOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products. -march=znver4 enables AVX 512 ISA for Genoa (znver4) processors.
-
-
- -ffast-math
- CXXOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
-
-
-
-
- -zopt
- CXXOPTIMIZE
-
This option enables a subset of scalar, vector and loop transformations including improved variants of loop invariant code motion, SLP and loop vectorizations, loop-fusion, loop-interchange, loop-unswitch, loop tiling and loop distribution.
-
-
-
-
-
-
- -m64
- FC, LD
-
Generates code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -O3
- FOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver4
- FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products. -march=znver4 enables AVX 512 ISA for Genoa (znver4) processors.
-
-
- -ffast-math
- FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
-
-
-
-
-
-
-
Peak Optimization Flags
-
- -m32
- CC, LD
-
Generates code for a 32-bit environment. The 32-bit environment sets int, long and
pointer to 32 bits and generates code that runs on any i386 system. The compiler generates x86 or IA32
32-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
- -march=znver4
- COPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products. -march=znver4 enables AVX 512 ISA for Genoa (znver4) processors.
-
-
- -ffast-math
- COPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -fstruct-layout=7
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled, if dead or redundant fields can be deleted, and if
the pointer or integer fields in the structure can be compressed. If feasible, this optimization transforms the code to
enable these improvements. This transformation is likely to improve cache utilization and memory bandwidth. It is expected
to improve the scalability of programs executed on multiple cores.
This is effective only under flto as the whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application; with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=0: disables structure peeling (default).
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of 64-bit integer type to 32-bit integer type. This is performed under a
strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of 64-bit integer type to 32-bit integer type. This is performed under a strict safety
check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit integer type to 16-bit integer type. This is performed under a strict
safety check.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit integer type to 16-bit integer type. This is performed under a strict
safety check.
- fstruct-layout=8: enables structure peeling, pointer compression, 64 bit integer type compression
as in level 6 and creates optimal ordering of peeled structure fields which could improve runtime performance.
- fstruct-layout=9: enables structure peeling, pointer compression, 64 bit integer type compression
as in level 7 and creates optimal ordering of peeled structure fields which could improve runtime performance.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of 64-bit integer fields to 32-bit integer fields in structures. Going from
fstruct-layout=4 to fstruct-layout=5 may result in higher performance if the pointer values are such that the pointers
can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstructlayout=3 respectively, with the
added feature of safe compression of 64 bit integer fields to 16 bit integer in structures. Going from fstruct-layout=6
to fstruct-layout=7 may result in higher performance if the pointer values are such that the pointers can be
compressed to 16-bits.
-
-
-
-
-
-
- -zopt
- COPTIMIZE
-
This option enables a subset of scalar, vector and loop transformations including improved variants of loop invariant code motion, SLP and loop vectorizations, loop-fusion, loop-interchange, loop-unswitch, loop tiling and loop distribution.
-
- EXTRA_CFLAGS
-
In the 502/602.gcc benchmark description,
"multiple definitions of symbols" is listed under the "Known Portability Issues" section, and this option is one of the
suggested workarounds. This option causes Clang to revert to the same inlining behavior that GCC does when in pre-C99
mode.
-
-
- -m64
- CC, LD
-
Generates code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
- -march=znver4
- COPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products. -march=znver4 enables AVX 512 ISA for Genoa (znver4) processors.
-
-
- -ffast-math
- COPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -fstruct-layout=7
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled, if dead or redundant fields can be deleted, and if
the pointer or integer fields in the structure can be compressed. If feasible, this optimization transforms the code to
enable these improvements. This transformation is likely to improve cache utilization and memory bandwidth. It is expected
to improve the scalability of programs executed on multiple cores.
This is effective only under flto as the whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application; with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=0: disables structure peeling (default).
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of 64-bit integer type to 32-bit integer type. This is performed under a
strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of 64-bit integer type to 32-bit integer type. This is performed under a strict safety
check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit integer type to 16-bit integer type. This is performed under a strict
safety check.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit integer type to 16-bit integer type. This is performed under a strict
safety check.
- fstruct-layout=8: enables structure peeling, pointer compression, 64 bit integer type compression
as in level 6 and creates optimal ordering of peeled structure fields which could improve runtime performance.
- fstruct-layout=9: enables structure peeling, pointer compression, 64 bit integer type compression
as in level 7 and creates optimal ordering of peeled structure fields which could improve runtime performance.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of 64-bit integer fields to 32-bit integer fields in structures. Going from
fstruct-layout=4 to fstruct-layout=5 may result in higher performance if the pointer values are such that the pointers
can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstructlayout=3 respectively, with the
added feature of safe compression of 64 bit integer fields to 16 bit integer in structures. Going from fstruct-layout=6
to fstruct-layout=7 may result in higher performance if the pointer values are such that the pointers can be
compressed to 16-bits.
-
-
-
-
-
-
- -zopt
- COPTIMIZE
-
This option enables a subset of scalar, vector and loop transformations including improved variants of loop invariant code motion, SLP and loop vectorizations, loop-fusion, loop-interchange, loop-unswitch, loop tiling and loop distribution.
-
-
-
-
- -m64
- CXX, LD
-
Generates code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
- -O3
- CXXOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver4
- CXXOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products. -march=znver4 enables AVX 512 ISA for Genoa (znver4) processors.
-
-
- -ffast-math
- CXXOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
-
-
-
-
- -zopt
- CXXOPTIMIZE
-
This option enables a subset of scalar, vector and loop transformations including improved variants of loop invariant code motion, SLP and loop vectorizations, loop-fusion, loop-interchange, loop-unswitch, loop tiling and loop distribution.
-
-
-
-
-
- -m64
- CXX, LD
-
Generates code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
- -march=znver4
- CXXOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products. -march=znver4 enables AVX 512 ISA for Genoa (znver4) processors.
-
-
- -ffast-math
- CXXOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
-
-
-
- -zopt
- CXXOPTIMIZE
-
This option enables a subset of scalar, vector and loop transformations including improved variants of loop invariant code motion, SLP and loop vectorizations, loop-fusion, loop-interchange, loop-unswitch, loop tiling and loop distribution.
-
-
-
-
-
-
- -m64
- FC, LD
-
Generates code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
- -O3
- FOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver4
- FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products. -march=znver4 enables AVX 512 ISA for Genoa (znver4) processors.
-
-
- -ffast-math
- FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
-
-
-
-
-
-
-
Implicitly Included Flags
This section contains descriptions of flags that were included implicitly
by other flags, but which do not have a permanent home at SPEC.
-
- -O2
-
Moderate level of optimization which enables most optimizations. This is the default when no "-O" option is
specified, or if no value is specified (i.e. "-O").
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -O1
-
Somewhere between -O0 and -O2.
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
-
- -O3
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
Using numactl to bind processes and memory to cores
For multi-copy runs or single copy runs on systems with multiple sockets, it is advantageous to bind a process to a
particular core. Otherwise, the OS may arbitrarily move your process from one core to another. This can affect
performance. To help, SPEC allows the use of a "submit" command where users can specify a utility to use to bind
processes. We have found the utility 'numactl' to be the best choice.
numactl runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a
command and inherited by all of its children. The numactl flag "--physcpubind" specifies
which core(s) to bind the process. "-l" instructs numactl to keep a process's memory on the
local node while "-m" specifies which node(s) to place a process's memory. For full details on using
numactl, please refer to your Linux documentation, 'man numactl'
Note that some older versions of numactl incorrectly interpret application arguments as its own. For
example, with the command "numactl --physcpubind=0 -l a.out -m a", numactl will interpret
a.out's "-m" option as its own "-m" option. To work around this problem, we put
the command to be run in a shell script and then run the shell script using numactl. For example:
"echo 'a.out -m a' > run.sh ; numactl --physcpubind=0 bash run.sh"
numactl --interleave=all runcpu
numactl --interleave=all runcpu executes the SPEC CPU command runcpu so that memory is consumed across NUMA nodes rather than consumed from a single node. This helps prevent local node out-of-memory conditions which can occur when runcpu is executed without interleaving.
For full details on using numactl, please refer to your Linux documentation, 'man numactl'
Transparent Huge Pages (THP)
THP is an abstraction layer that automates most aspects of creating, managing,
and using huge pages. It is designed to hide much of the complexity in using
huge pages from system administrators and developers. Huge pages
increase the memory page size from 4 kilobytes to 2 megabytes. This provides
significant performance advantages on systems with highly contended resources
and large memory workloads. If memory utilization is too high or memory is badly
fragmented which prevents huge pages being allocated, the kernel will assign
smaller 4k pages instead. Most recent Linux OS releases have THP enabled by default.
THP usage is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/enabled.
Possible values:
- never: entirely disable THP usage.
- madvise: enable THP usage only inside regions marked MADV_HUGEPAGE using madvise(3).
- always: enable THP usage system-wide. This is the default.
The SPEC CPU benchmark codes themselves never explicitly request huge pages, as the mechanism to do that is OS-specific
and can change over time. Libraries such as amdalloc which are used by the benchmarks may explicitly request huge pages,
and use of such libraries can make the "madvise" setting relevant and useful.
When no huge pages are immediately available and one is requested, how the system handles the request for THP creation is
controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/defrag.
Possible values:
- never: if no THP are available to satisfy a request, do not attempt to make any.
- defer: an allocation requesting THP when none are available gets normal pages while requesting THP creation in the
background.
- defer+madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3); for all
other regions it's like "defer".
- madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3). This is the
default.
- always: an allocation requesting THP when none are available will stall until some are made.
An application that "always" requests THP often can benefit from waiting for an allocation until those huge pages can be assembled.
For more information see the Linux transparent hugepage documentation.
ulimit -s <n>
Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.
ulimit -l <n>
Sets the maximum size of memory that may be locked into physical memory.
powersave -f (on SuSE)
Makes the powersave daemon set the CPUs to the highest supported frequency.
/etc/init.d/cpuspeed stop (on Red Hat)
Disables the cpu frequency scaling program in order to set the CPUs to the highest supported frequency.
LD_LIBRARY_PATH
An environment variable that indicates the location in the filesystem of bundled libraries to use when running the
benchmark binaries.
LIBOMP_NUM_HIDDEN_HELPER_THREADS
target nowait is supported via hidden helper task, which is a task not bound to any parallel region. A hidden helper team with a number of threads is created when the first hidden helper task is encountered.
The number of threads can be configured via the environment variable LIBOMP_NUM_HIDDEN_HELPER_THREADS. The default is 8. If LIBOMP_NUM_HIDDEN_HELPER_THREADS is 0, the hidden helper task is disabled and support falls back to a regular OpenMP task. The hidden helper task can also be disabled by setting the environment variable LIBOMP_USE_HIDDEN_HELPER_TASK=OFF.
sysctl -w vm.dirty_ratio=8
Limits dirty cache to 8% of memory.
sysctl -w vm.swappiness=1
Limits swap usage to minimum necessary.
sysctl -w vm.zone_reclaim_mode=1
Frees local node memory first to avoid remote memory usage.
kernel/numa_balancing
This OS setting controls automatic NUMA balancing on memory mapping and process placement.
NUMA balancing incurs overhead for no benefit on workloads that are already bound to NUMA nodes.
Possible settings:
- 0: disables this feature
- 1: enables the feature (this is the default)
For more information see the numa_balancing entry in the
Linux sysctl documentation.
kernel/randomize_va_space (ASLR)
This setting can be used to select the type of process address space
randomization. Defaults differ based on whether the architecture supports
ASLR, whether the kernel was built with the CONFIG_COMPAT_BRK
option or not, or the kernel boot options used.
Possible settings:
- 0 - Turn the process address space randomization off. This is the default for architectures that do not support
this feature anyway, and kernels that are booted with the "
norandmaps" parameter.
- 1 - Randomize addresses of mmap base, stack, and VDSO pages.
This is the default if the
CONFIG_COMPAT_BRK option is enabled at kernel build time.
- 2 - Additionally enable heap randomization. This is the default if
CONFIG_COMPAT_BRK is
disabled.
Disabling ASLR can make process execution more deterministic and runtimes more consistent.
For more information see the randomize_va_space entry in the
Linux sysctl documentation.
vm/drop_caches
The two commands are equivalent:
echo 3> /proc/sys/vm/drop_caches
and
sysctl -w vm.drop_caches=3
Both must be run as root.
The commands are used to free up the filesystem page cache, dentries, and inodes.
Possible settings:
- 1 - Clear pagecache
- 2 - Clear dentries and inodes
- 3 - Clear pagecache, dentries, and inodes
MALLOC_CONF
The amdalloc library is a variant of jemalloc library. The amdalloc
library has tunable parameters, many of which may be changed at run-time via several mechanisms, one of which
is the MALLOC_CONF environment variable. Other methods, as well as the order in which they're referenced,
are detailed in the jemalloc documentation's TUNING section.
The options that can be tuned at run-time are everything in the jemalloc documentation's
MALLCTL NAMESPACE section that begins with
"opt.".
The options that may be encountered in SPEC CPU 2017 results are detailed here:
retain:true - Causes unused virtual memory to
be retained for later reuse rather than discarding it. This is the default for 64-bit Linux.thp:never - Attempts to never utilize huge pages
by using MADV_NOHUGEPAGE on all mappings. This option has no effect except when THP is set to
"madvise".
PGHPF_ZMEM
An environment variable used to initialize the allocated memory. Setting PGHPF_ZMEM to "Yes" has the effect of
initializing all allocated memory to zero.
GOMP_CPU_AFFINITY
This environment variable is used to set the thread affinity for threads spawned by OpenMP.
OMP_DYNAMIC
This environment variable is defined as part of the OpenMP standard.
Setting it to "false" prevents the OpenMP runtime from dynamically adjusting the number of threads to use for parallel
execution.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
OMP_SCHEDULE
This environment variable is defined as part of the OpenMP standard.
Setting it to "static" causes loop iterations to be assigned to threads in round-robin fashion in the order of the thread
number.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
OMP_STACKSIZE
This environment variable is defined as part of the OpenMP standard and controls the size of the stack for threads created
by OpenMP.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
OMP_THREAD_LIMIT
This environment variable is defined as part of the OpenMP standard and limits the maximum number of OpenMP threads that
can be created.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
- cpupower:
-
The OS 'cpupower' utility is used to change CPU power governors settings. Available settings are:
- Performance: Run the CPU at the maximum frequency.
- powersave(default): Run the CPU at the minimum frequency.
- ondemand: Scales the frequency dynamically according to current load. Jumps to the highest frequency and then possibly back off as the idle time increases.
- drop_caches:
-
sysctl is used to change kernel parameters at run-time
-w vm.drop_caches=3 - clears filesystem caches
- SCALING_GOVERNOR:
-
Setting this environment variable to "performance" to enable cores to run at performance mode.
"scaling_governor" is a configuration file in Linux's "cpufreq" model. There are five mode in "scaling_governor" which are performance, powersave, userspace, ondemand, and conservative.
- Performance: Lock the CPU's frequency at top speed without adjusting dynamically,which may require additional power;
- Powersave: CPU will work at the minimum frequency;
- Userspace: Provides the corresponding interface for the user-mode application program to adjust the frequency of CPU;
- Ondemand: Quick dynamic adjustment of CPU frequency on demand, and will reach the maximum frequency;
- Conservative: Frequency will be adjusted on demand.
We use "cpupower frequency-set -g performance" to set this environment variable to "performance".
- kernel.randomize_va_space (ASLR):
-
This setting can be used to select the type of process address space randomization.
Defaults differ based on whether the architecture supports ASLR, whether the kernel
was built with the CONFIG_COMPAT_BRK option or not, or the kernel boot options used.
Possible settings:
- 0: Turn process address space randomization off.
- 1: Randomize addresses of mmap base, stack, and VDSO pages.
- 2: Additionally randomize the heap. (This is probably the default.)
Disabling ASLR can make process execution more deterministic and runtimes more consistent.
For more information see the randomize_va_space entry in the
Linux sysctl documentation.
- Transparent Hugepages (THP):
-
THP is an abstraction layer that automates most aspects of creating, managing,
and using huge pages. It is designed to hide much of the complexity in using
huge pages from system administrators and developers. Huge pages
increase the memory page size from 4 kilobytes to 2 megabytes. This provides
significant performance advantages on systems with highly contended resources
and large memory workloads. If memory utilization is too high or memory is badly
fragmented which prevents hugepages being allocated, the kernel will assign
smaller 4k pages instead. Most recent Linux OS releases have THP enabled by default.
THP usage is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/enabled.
Possible values:
- never: entirely disable THP usage.
- madvise: enable THP usage only inside regions marked MADV_HUGEPAGE using madvise(3).
- always: enable THP usage system-wide. This is the default.
THP creation is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/defrag.
Possible values:
- never: if no THP are available to satisfy a request, do not attempt to make any.
- defer: an allocation requesting THP when none are available get normal pages while requesting THP creation in the background.
- defer+madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3); for all other regions it's like "defer".
- madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3). This is the default.
- always: an allocation requesting THP when none are available will stall until some are made.
An application that "always" requests THP often can benefit from waiting for an allocation until those huge pages can be assembled.
For more information see the Linux transparent hugepage documentation.
- tuned-adm:
-
A commandline interface for switching between different tuning profiles available in supported Linux distributions. The distribution provided profiles are located in /usr/lib/tuned and the user defined profiles in /etc/tuned. To set a profile, one can issue the command "tuned-adm profile (profile_name)". Below are details about some relevant profiles.
- tuned-adm command line utility allows user to switch between user definable tuning profiles.[active, profile (name), off]
- throughput-performance: For typical throughput performance tuning. Disables power saving mechanisms and enables sysctl settings that improve the throughput performance of disk and network I/O. CPU governor is set to performance and CPU energy performance bias is set to performance. Disk readahead values are increased;
- latency-performance: For low latency performance tuning. Disables power saving mechanisms. CPU governor is set to performance and locked to the low C states. CPU energy performance bias to performance;
- balanced: Default profile provides balanced power saving and performance. It enables CPU and disk plugins of tuned and makes the conservative governor is active and also sets the CPU energy performance bias to normal. It also enables power saving on audio and graphics card;
- powersave: Maximal power saving for whole system. It sets the CPU governor to ondemand governor and energy performance bias to powersave. It also enable power saving on USB, SATA, audio and graphics card;
We use "tuned-adm profile throughput-performance" to set this environment variable to "throughput-performance".
- SMT Mode
-
Can be used to disable symmetric multithreading. To re-enable SMT, a POWER CYCLE is needed after selecting Enable..
- Enable: Enables simultaneous multithreading.
- Disable: Disables simultaneous multithreading so that only one thread or CPU instruction stream is run on a physical CPU core.
- Determinism Slider:
-
This BIOS option allows for AGESA determinism to control performance.
- Performance: Provides predictable performance across all processors of the same type.
- Power: Maximizes performance within the power limits defined by cTDP and PPT.
- Auto (Default setting): Use AGESA default value for deterministic performance control.
- cTDP Control:
-
This BIOS option is for "Configurable TDP (cTDP)", it allows user can set customized value for TDP. Available settings are:
- Auto: Use the fused TDP value.
- Manual(Default setting): Let user specifies customized TDP value.
- cTDP:
-
TDP is an acronym for "Thermal Design Power." TDP is the recommended target for power used when designing the cooling capacity for a server.
EPYC processors are able to control this target power consumption within certain limits. This capability is referred to as "configurable TDP" or "cTDP."
cTDP can be used to reduce power consumption for greater efficiency, or in some cases, increase power consumption above the default value to provide additional performance.
cTDP is controlled using a BIOS option.
The default EPYC cTDP value corresponds with the microprocessor's nominal TDP.
The default cTDP value is set at a good balance between performance and energy efficiency.
- Power phase shedding:
-
Power phase shedding allows efficiency optimization of the voltage regulator across the variety of loads, minimizing average energy consumption by optimizing the powertrain for specific load power states.
Values for this BIOS option can be: Enabled/Disabled. Current default is Enabled.
- SVM Mode:
-
This is CPU virtualization function. With SVM enabled you'll be able to install a virtual machine on your system.
Values for this BIOS option can be: Enabled/Disabled. Current default is Enabled.
- SR-IOV support:
-
In virtualization, single root input/output virtualization or SR-IOV is a specification that allows the isolation of the PCI Express resources for manageability and performance reasons.
A single physical PCI Express can be shared on a virtual environment using the SR-IOV specification.
If system has SR-IOV capable PCIe Devices, this option Enables or Disables Single Root IO Virtualization Support. Values for this BIOS option can be: Enabled/Disabled. Current default is Disabled.
- DRAM Scrub time:
-
DRAM scrubbing is a mechanism for the memory controller to periodically read all memory locations and write back corrected data.
The time interval for scrubbing the entire memory can be: Disabled/1 hour/4 hours/8 hours/16 hours/24 hours/48 hours/Auto. Current default is Auto(AGESA default value).
- NUMA nodes per socket:
-
Specifies the number of desired NUMA nodes per populated socket in the system:
- NPS1: Each physical processor is a NUMA node, and memory accesses are interleaved across all memory channels directly connected to the physical processor.
- NPS2: Each physical processor is two NUMA nodes, and memory accesses are interleaved across 4 memory channels.
- NPS4: Each physical processor is four NUMA nodes, and memory accesses are interleaved across 2 memory channels.
- Auto: Use AGESA default value. Current default is NPS1
Current default is Auto.
- APBDIS:
-
Application Power Management (APM) allows the processor to provide maximum performance while remaining within
the specified power delivery and removal envelope. APM dynamically monitors processor activity and generates an
approximation of power consumption. If power consumption exceeds a defined power limit, a P-state limit is applied by
APM hardware to reduce power consumption. APM ensures that average power consumption over a thermally significant
time period remains at or below the defined power limit. Set APBDIS=1 will disable Data Fabric APM and the SOC P-state will be fixed.
Available settings are:
- 0: Disable APBDIS.
- 1: Enable APBDIS.
- Auto (Default setting): Use default value for APBDIS. The current value is 0.
- Fix SOC P-state:
-
To minimize variance or trade-off memory latency versus bandwidth, algorithm performance boost
(APBDIS) can be set and specific hard-fused Data Fabric (SoC) P-states forced for optimized
workloads sensitive to latency or throughput.
Available settings are:
- P0: The highest SOC P-state.
- P1
- P2
- P3: The lowest SOC P-state.
- Auto (Default setting): Use AGESA default value.
- ACPI SRAT L3 Cache as NUMA Domain:
-
Each L3 Cache will be exposed as a NUMA node when enabling ACPI SRAT L3 Cache as a NUMA node.
On a dual processor system, with up to 8 L3 Caches per processor, this setting will expose 16 NUMA domains.
Available settings are:
- Auto (Default setting): Disable this function.
- Enabled: Enable this function.
- Package Power Limit Control:
-
This BIOS option allows user can set customized value for processor package power limit(PPT). Available settings are:
- Auto: Use the fused PPT.
- Manual(Default setting): User can set customized PPT.
- DLWM Support:
-
Dynamic Link Width Management(DLWM) reduces xGMI lane width from x16 to x8 or x2 if xGMI links have limited traffic. DLWM feature is optimized to
trade power between CPU core intensive workloads and I/O bandwidth intensiveworkloads. When link activity is above a threshold, DLWM will
increase lane width from x8 to x16 at the cost of some delay, because the I/O die must disconnect the links, retrain them at the new speed
and release the system back to functionality.
Values for this BIOS option can be: Auto/Enabled/Disabled. Current default is Auto.(Use AGESA default value. Current is Enabled.)
- Engine Boost:
-
ASUS individual feature with the power acceleration design to increase CPU over-all performance. Available settings are: disabled(default) and enabled.
Enable it could improve performance, but comes with more power consumption.
- Package Power Limit:
-
Set customize processor Package Power Limit (PPT) value to be used on all populated processors in the system. Current default value is 240 = Use the 240W PPT value.
***PPT will be used as the ASIC power limit***
- IOMMU:
-
The Input-Output Memory Management Unit(IOMMU) provides several benefits and is required when using x2APIC. Enabling the IOMMU allows devices
(such as the EPYC integrated SATA controller) to present separate IRQs for each attached device instead of one IRQ for the subsystem.
The IOMMU also allows operating systems to provide additional protection for DMA capable I/O devices.
Values for this BIOS option can be: Auto/Enabled/Disabled. Current default is Auto.(Use AGESA default value. Current is Enabled.)
- Memory Interleaving:
-
Memory interleaving is a technique that CPUs use to increase the memory bandwidth available for an
application. Without interleaving, consecutive memory blocks, often cache lines, are read from the
same memory bank. Because of this, software that reads consecutive memory must wait for a
memory transfer to complete before starting the next memory access, reducing throughput and
increasing latency. By enabling memory interleaving, consecutive memory blocks are in different
banks and can all contribute to the overall memory bandwidth, thus increasing throughput and lowering latency.
Values for this BIOS option can be: Auto/Disabled. Current default is Auto.(Use AGESA default value. Current is Enabled.)
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2024 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.1.9.
Report generated on 2024-05-21 19:25:12 by SPEC CPU2017 flags formatter v5178.
![[benchmark]](https://www.spec.org/auto/cpu2017/images/benchmark.png)