CPU2017 Flag Description
Hewlett Packard Enterprise ProLiant DL380p Gen8 (2.50 GHz, Intel Xeon E5-2670 v2)

Test sponsored by HPE

Copyright © 2016 Intel Corporation. All Rights Reserved.

Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.

• • -O3
  • 

  • Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:

    • Loop unrolling, including instruction scheduling
    • Code replication to eliminate branches
    • Padding the size of certain power-of-two arrays to allow more efficient cache use.
    
    

    On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.

  • Includes:
    • -O2
      • -O1
        • -funroll-loops
        • -fno-builtin
        • -mno-ieee-fp
        • -fomit-framepointer
        • -ffunction-sections
        • -ftz
• • -O2
  • 

  • Enable optimizations for speed. This is the generally recommended optimization level. This option also enables:
    - Inlining of intrinsics
    - Intra-file interprocedural optimizations, which include:
    - inlining
    - constant propagation
    - forward substitution
    - routine attribute propagation
    - variable address-taken analysis
    - dead static function elimination
    - removal of unreferenced variables
    - The following capabilities for performance gain:
    - constant propagation
    - copy propagation
    - dead-code elimination
    - global register allocation
    - global instruction scheduling and control speculation
    - loop unrolling
    - optimized code selection
    - partial redundancy elimination
    - strength reduction/induction variable simplification
    - variable renaming
    - exception handling optimizations
    - tail recursions
    - peephole optimizations
    - structure assignment lowering and optimizations
    - dead store elimination
    

  • Includes:
    • -O1
      • -funroll-loops
      • -fno-builtin
      • -mno-ieee-fp
      • -fomit-framepointer
      • -ffunction-sections
      • -ftz
• • -O1
  • 

  • Enable optimizations for speed and disables some optimizations that increase code size and affect speed.
    To limit code size, this option:

    • Enable global optimization; this includes data-flow analysis, code motion, strength reduction and test replacement, split-lifetime analysis, and instruction scheduling.
    • Disables intrinsic recognition and intrinsics inlining.

    The O1 option may improve performance for applications with very large code size, many branches, and execution time not dominated by code within loops.

    -O1 sets the following options:
    -funroll-loops0, -fno-builtin, -mno-ieee-fp, -fomit-framepointer, -ffunction-sections, -ftz
  • Includes:
    • -funroll-loops
    • -fno-builtin
    • -mno-ieee-fp
    • -fomit-framepointer
    • -ffunction-sections
    • -ftz
• • -funroll-loops
  • 

  • Tells the compiler the maximum number of times to unroll loops. For example -funroll-loops0 would disable unrolling of loops.

• • -fno-builtin
  • 

  • -fno-builtin disables inline expansion for all intrinsic functions.

• • -mno-ieee-fp
  • 

  • This option trades off floating-point precision for speed by removing the restriction to conform to the IEEE standard.

• • -fomit-framepointer
  • 

  • EBP is used as a general-purpose register in optimizations.

• • -ffunction-sections
  • 

  • Places each function in its own COMDAT section.

• • -ftz
  • 

  • Flushes denormal results to zero.

Commands and Options Used to Submit Benchmark Runs

submit= MYMASK=`printf '0x%x' $((1<<$SPECCOPYNUM))`; /usr/bin/taskset $MYMASK $command

When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command, using taskset, is used for Linux64 systems without numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:

• /usr/bin/taskset [options] [mask] [pid | command [arg] ... ]:
  taskset is used to set or retreive the CPU affinity of a running process given its PID or to launch a new COMMAND with a given CPU affinity. The CPU affinity is represented as a bitmask, with the lowest order bit corresponding to the first logical CPU and highest order bit corresponding to the last logical CPU. When the taskset returns, it is guaranteed that the given program has been scheduled to a specific, legal CPU, as defined by the mask setting.
• [mask]: The bitmask (in hexadecimal) corresponding to a specific SPECCOPYNUM. The specific example above, computes this mask value in the variable $MYMASK. The value of this mask for the first copy of a rate run will be 0x00000001, for the second copy of the rate will be 0x00000002 etc. Thus, the first copy of the rate run will have a CPU affinity of CPU0, the second copy will have the affinity CPU1 etc.
• $command: Program to be started, in this case, the benchmark instance to be started.

submit= numactl --localalloc --physcpubind=$SPECCOPYNUM $command

When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command is used for Linux64 systems with support for numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:

• syntax: numactl [--interleave=nodes] [--preferred=node] [--physcpubind=cpus] [--cpunodebind=nodes] [--membind=nodes] [--localalloc] command args ...
• numactl runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a command and inherited by all of its children.
• "--localalloc" instructs numactl to keep a process memory on the local node while "-m" specifies which node(s) to place a process memory.
• "--physcpubind" specifies which core(s) to bind the process. In this case, copy 0 is bound to processor 0 etc.
• For full details on using numactl, please refer to your Linux documentation, 'man numactl'

Shell, Environment, and Other Software Settings

numactl --interleave=all "runspec command"

Launching a process with numactl --interleave=all sets the memory interleave policy so that memory will be allocated using round robin on nodes. When memory cannot be allocated on the current interleave target fall back to other nodes.

KMP_STACKSIZE

Specify stack size to be allocated for each thread.

KMP_AFFINITY

Syntax: KMP_AFFINITY=[<modifier>,...]<type>[,<permute>][,<offset>]
The value for the environment variable KMP_AFFINITY affects how the threads from an auto-parallelized program are scheduled across processors.
It applies to binaries built with -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows).
modifier:
    granularity=fine Causes each OpenMP thread to be bound to a single thread context.
type:
    compact Specifying compact assigns the OpenMP thread <n>+1 to a free thread context as close as possible to the thread context where the <n> OpenMP thread was placed.
    scatter Specifying scatter distributes the threads as evenly as possible across the entire system.
permute: The permute specifier is an integer value controls which levels are most significant when sorting the machine topology map. A value for permute forces the mappings to make the specified number of most significant levels of the sort the least significant, and it inverts the order of significance.
offset: The offset specifier indicates the starting position for thread assignment.

Please see the Thread Affinity Interface article in the Intel Composer XE Documentation for more details.

Example: KMP_AFFINITY=granularity=fine,scatter
Specifying granularity=fine selects the finest granularity level and causes each OpenMP or auto-par thread to be bound to a single thread context.
This ensures that there is only one thread per core on cores supporting HyperThreading Technology
Specifying scatter distributes the threads as evenly as possible across the entire system.
Hence a combination of these two options, will spread the threads evenly across sockets, with one thread per physical core.

Example: KMP_AFFINITY=compact,1,0
Specifying compact will assign the n+1 thread to a free thread context as close as possible to thread n.
A default granularity=core is implied if no granularity is explicitly specified.
Specifying 1,0 sets permute and offset values of the thread assignment.
With a permute value of 1, thread n+1 is assigned to a consecutive core. With an offset of 0, the process's first thread 0 will be assigned to thread 0.
The same behavior is exhibited in a multisocket system.

OMP_NUM_THREADS

Sets the maximum number of threads to use for OpenMP* parallel regions if no other value is specified in the application. This environment variable applies to both -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores: export OMP_NUM_THREADS=8

Set stack size to unlimited

The command "ulimit -s unlimited" is used to set the stack size limit to unlimited.

Free the file system page cache

The command "echo 3> /proc/sys/vm/drop_caches" is used to free up the filesystem page cache as well as reclaimable slab objects like dentries and inodes.

Red Hat Specific features

Transparent Huge Pages

On RedHat EL 6 and later, Transparent Hugepages increase the memory page size from 4 kilobytes to 2 megabytes. Transparent Hugepages provide significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead.
Hugepages are used by default unless the /sys/kernel/mm/redhat_transparent_hugepage/enabled field is changed from its RedHat EL6 default of 'always'.

Operating System Tuning Parameters

OS Tuning

Using numactl to bind processes and memory to cores

For multi-copy runs or single copy runs on systems with multiple sockets, it is advantageous to bind a process to a particular core. Otherwise, the OS may arbitrarily move your process from one core to another. This can effect performance. To help, SPEC allows the use of a "submit" command where users can specify a utility to use to bind processes. We have found the utility 'numactl' to be the best choice.

numactl runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a command and inherited by all of its children. The numactl flag "--physcpubind" specifies which core(s) to bind the process. "-l" instructs numactl to keep a process memory on the local node while "-m" specifies which node(s) to place a process memory. For full details on using numactl, please refer to your Linux documentation, 'man numactl'

numactl --interleave=all "runspec command"

Launching a process with numactl --interleave=all sets the memory interleave policy so that memory will be allocated using round robin on nodes. When memory cannot be allocated on the current interleave target fall back to other nodes.

Transparent Huge Pages

On RedHat EL 6 and later, Transparent Hugepages increase the memory page size from 4 kilobytes to 2 megabytes. Transparent Hugepages provide significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead. Hugepages are used by default if /sys/kernel/mm/redhat_transparent_hugepage/enabled is set to always.

Drive Write Cache

The Drive Write Cache is an option that can be enabled or disabled in the HP Array Configuration Utility, CLI version. The default value for the Drive Write Cache is set to Disabled, and in order to change this the HP Arracy Configuration Utility, CLI version needs to be installed. When the Drive Write Cache option is enabled on a HP Smart Arrary Controller in a system, it can allow the HP Smart Array Controller to help make drive writes more efficient.

Accelerator Ratio

The Accelerator Ratio is an option that can be set to different percentages (in 25% increments) in the HP Array Configuration Utility, CLI version. The default value for the Accelerator Ratio is set to 0% Read and 100% Write. In order to change this the HP Arracy Configuration Utility, CLI version needs to be installed. Changing the Accelerator Ratio allows the array installed on the HP Smart Arrary Controller to adjust how it priotizes reads and writes.

ulimit -s [n | unlimited] (Linux)

Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.

KMP_STACKSIZE=integer[B|K|M|G|T] (Linux)

Sets the number of bytes to allocate for each parallel thread to use as its private stack. Use the optional suffix B, K, M, G, or T, to specify bytes, kilobytes, megabytes, gigabytes, or terabytes. The default setting is 2M on IA32 and 4M on IA64.

KMP_AFFINITY=physical,n (Linux)

Assigns threads to consecutive physical processors (for example, cores), beginning at processor n. Specifies the static mapping of user threads to physical cores, beginning at processor n. For example, if a system is configured with 8 cores, and OMP_NUM_THREADS=8 and KMP_AFFINITY=physical,2 are set, then thread 0 will mapped to core 2, thread 1 will be mapped to core 3, and so on in a round-robin fashion.

OMP_NUM_THREADS=n

This Environment Variable sets the maximum number of threads to use for OpenMP* parallel regions to n if no other value is specified in the application. This environment variable applies to both -openmp and -parallel (Linux) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores:
export OMP_NUM_THREADS=8
Default is the number of cores visible to the OS.

vm.max_map_count-n (Linux)

The maximum number of memory map areas a process may have. Memory map areas are used as a side-effect of calling malloc, directly by mmap and mprotect, and also when loading shared libraries.

Disabled unused Linux services via stop_services.sh script.

The following unused Linux services were disabled before the run in simple shell scirpt via the command "service {name} stop": abrt-ccpp, abrt-oops, abrtd, acpid, atd, auditd, autofs, avahi-daemon, cgconfig, cpuspeed, crond, cups, haldaemon, irqbalance, kdump, libvirt-guests, mcelogd, mdmonitor, messagebus, portreserve, postfix, rhnsd, rhsmcertd, rpcbind, rpcgssd, rpcidmapd, certmonger, lvm2-monitor, netfs, and sysstat.

Firmware / BIOS / Microcode Settings

Firmware Settings

One or more of the following settings may have been set. If so, the "Platform Notes" section of the report will say so; and you can read below to find out more about what these settings mean.

Intel Hyperthreading Options (Default = Enabled):

This feature allows enabling/disabling of logical processor cores on processors supporting Intel's Hyper-Threading Technology. This option may improve overall performance for applications that will benefit from higher processor core count.

Processor Core Disable (Intel Core Select) (Default = number of physical cores/processor):

This feature allows disabling of processor cores using Intel's Core Multi-Processing (CMP) Technology. This option allows disabling of a specific number of the cores on each physical processor. This option has the following potential uses: Reduce processor power usage and potentially improve performance/watt with some applications; improve overall performance for applications that will benefit from higher performance cores rather than more processing cores; address issues with software that is licensed on a per-core basis.

The value entered should be the number of enabled cores per socket. Valid values are 1 to 12 where 1 indicates that one core will be ENABLED per processor socket. A value of 0 is invalid as the minimum number of enabled cores per processor socket is 1.

HP Power Profile (Default = Balanced Power and Performance):

Values for this BIOS setting can be:

• Balanced Power and Performance: Provides the optimum settings to maximize power savings with minimal impact to performance for most Operating Systems and applications.
• Minimum Power Usage: Enables power reduction mechanisms that may negatively affect performance. This mode will guarantee a lower maximum power usage by the system.
• Maximum Performance: Disables all power management options that may negatively affect performance.
• Custom:Allows the user to customize power management options independent of the defaults that each preset Power Profile sets. The HP Power Profile also will automatically change to this value if a power management option such as Energy/Performance Bias, Collaborative Power Control, or Processor Power and Utilization Monitoring is changed from the default value that is associated with one of the preset Power Profiles.

Power Regulator for ProLiant support (Default=HP Dynamic Power Savings Mode)

Values for this BIOS setting can be:

• HP Dynamic Power Savings Mode: Automatically varies processor speed and power usage based on processor utilization. Allows reducing overall power consumption with little or no impact to performance. Does not require OS support.
• HP Static Low Power Mode: Reduces processor speed and power usage. Guarantees a lower maximum power usage for the system. Performance impacts will be greater for environments with higher processor utilization.
• HP Static High Performance Mode: Processors will run in their maximum power/performance state at all times regardless of the OS power managment policy.
• OS Control Mode: Processors will run in their maximum power/ performance state at all times unless the OS enables' a power management policy.

Minimum Processor Idle Power Core State (Default (w/HP Power Profile=Maximum Performance)=No C-states):

This feature selects the processor's lowest idle core power state (C-state) which the operating system will utilize. The higher the C-State, the lower the power usage of that idle state (Core C6 is the lowest power idle core state supported by the processor). Values for this setting can be:

• C6 State: While in C6, the core PLLs are turned off, the core caches are flushed and the core state is saved to the Last Level Cache. Power Gates are used to reduce power consumption to close to zero. C6 is considered an inactive core.
• C3 State: While in C3 the core PLLs are turned off, and all the core caches are flushed. C3 is considred an inactive core.
• C1E State: C1E is defined as the enhanced halt state. While in C1E no instructions are being executed. C1E considered an active core.
• No C-states: No C-states is defined as C0, which is defined as the active state. While in C0, instructions are being executed by the core.

Minimum Processor Idle Power Package State (Default (w/HP Power Profile=Maximum Performance)=No Package state):

This feature selects the processor's lowest idle package power state (C-state) which is enabled. The proecessor will automatically transition into the package C-states based on the Core C-states which cores on the processor have transitioned to. The higher the package C-state, the lower the power usage of that idle package state (Package C6 (retention) is the lowed power idle package state supported by the processor). Values for this setting can be:

• Package C6 (retention) State: All cores have saved their architectural state and have had their core voltages reduced to zero volts. The LLC retains context, but no accesses can be made to the LLC in this state, the cores must break out to the internaal state package C2 for snoops to occur.
• Package C6 (non-retention) State: All cores have saved their architectural state and have had their core voltages reduced to zero volts. The LLC does not retain context, and no accesses can be made to the LLC in this state, the cores must break out to the internaal state package C2 for snoops to occur.
• No Package State: All cores are in an active state and have not entered any power saving state.

Energy/Performance Bias (Default = Balanced Performance):

This option configures several processor subsystems to optimize the processor's performance and power usage. Values for this BIOS setting can be:

• Maximum Performance Mode: Should be used for environments that require the highes performance and lowest latency but are not sensitive to power consumption.
• Balanced Performance: Provides optimum performance efficiency.
• Balanced Power: Provieds optimum power efficiency and is recommended for most environments.
• Power Savings Mode: Should only be used in environments that are power sensitive and are willing to accept reduced performance.

Collaborative Power Control (Default = Enabled):

This BIOS option allows the enabling/disabling of the Processor Clocking Controll (PCC) Interface, for operating systems which support this feature. Enabling this option allows the Operating System to request processor frequency changes even when the server has the Power Regulator option configured for Dynamic Power Savings Mode.

For Operating Systems that do not support the PCC Interface or when the Power Regulator Mode is not configured for Dynamic Power Savings Mode, this option has no impact on system operation.

Dynamic Power Capping Functionality (Default = Enabled):

This BIOS option allows the user to disable the System ROM Power Calibration feature that is executed during the boot process. When disabled, the user can expect faster boot times but will not be able to enable a Dynamic Power Cap until this feature is re-enabled.

Memory Power Savings Mode (Default = Balanced):

This option configures several memory parameters to optmizie the memory subsystems performance and power usage. Values for this BIOS setting can be:

• Balanced: Balanced provieds optimum power efficiency and is recommended for most environments.
• Maximum Performance: Maximum Performance Mode should be used for environments that require the highest performance and/or lowest latency but are not sensitive to power consumption.

Thermal Configuration (Default = Optimal Cooling):

This feature allows the user to select the fan cooling solution for the system. Values for this BIOS option can be:

• Optimal Cooling: Provides the most efficient solution by configuring fan speeds to the minimum required to provide adequate cooling.
• Increased Cooling: Will run fans at higher speeds to provide aditional cooling. Increased Cooling should be selected when non-HP storage controllers are cabled to the embedded hard drive cage, or if the system is experiencing thermal issues that cannot be resolved in another manner.
• Maximum Cooling: Will provide the maximum cooling available by this platform.

HW Prefetch (Default = Enabled):

This BIOS option allows allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern recognition algorithm.

In some limited cases, setting this option to Disabled may improve performance. In the majority of cases, the default value of Enabled provides better performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Adjacent Sector Prefetch (Default = Enabled):

This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within an 128-byte sector that contains the data needed due to a cache line miss.

In some limited cases, setting this option to Disabled may improve performance. In the majority of cases, the default value of Enabled provides better performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Processor Power and Utilization Monitoring (Default = Enabled):

This BIOS option allows the enabling/disabling of iLo4 Processor State Mode Switching and Insight Power Management Processor Utilization Monitoring.

When set to disabled, the system will also set the HP Power Regulator mode to HP Static High Performance mode and the HP Power Profile mode to Custom. This option may be useful in some environments that require absolute minimum latency.

Memory Refresh Rate (Default = 2x Refresh):

This BIOS option controls the refresh rate of the memory controller and may affect the performance and resiliency of the servers memory.

When set to 1x Refresh, the memory refresh rate will be decreased, the HP Power Regulator mode will be set to HP Static High Performance mode, and the HP Power Profile mode to Custom. This option may be useful in some environments that require absolute minimum latency.

When set to 3x Refresh, the memory refresh rate will be increased, the HP Power Regulator mode will be set to HP Static High Performance mode, and the HP Power Profile mode to Custom.

Last updated May 22, 2023.

Flag description origin markings:

	Indicates that the flag description came from the user flags file.
	Indicates that the flag description came from the suite-wide flags file.
	Indicates that the flag description came from a per-benchmark flags file.

For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2023 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.1.9.
Report generated on 2023-06-06 19:14:19 by SPEC CPU2017 flags formatter v5178.