CPU2017 Flag Description
Inspur Electronic Information Industry Co., Ltd. (IEI) NF5180M7 (Intel Xeon Silver 4416+)

Copyright © 2016 Intel Corporation. All Rights Reserved.

Base Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++

Peak Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++

Base Portability Flags

503.bwaves_r

507.cactuBSSN_r

508.namd_r

510.parest_r

511.povray_r

519.lbm_r

521.wrf_r

526.blender_r

527.cam4_r

538.imagick_r

544.nab_r

549.fotonik3d_r

554.roms_r

Peak Portability Flags

503.bwaves_r

507.cactuBSSN_r

508.namd_r

510.parest_r

511.povray_r

519.lbm_r

521.wrf_r

526.blender_r

527.cam4_r

538.imagick_r

544.nab_r

549.fotonik3d_r

554.roms_r

Base Optimization Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++

Peak Optimization Flags

C benchmarks

519.lbm_r

538.imagick_r

544.nab_r

C++ benchmarks

508.namd_r

510.parest_r

Fortran benchmarks

503.bwaves_r

549.fotonik3d_r

554.roms_r

Benchmarks using both Fortran and C

521.wrf_r

527.cam4_r

Benchmarks using both C and C++

511.povray_r

526.blender_r

Benchmarks using Fortran, C, and C++

Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.

Commands and Options Used to Submit Benchmark Runs

submit= MYMASK=`printf '0x%x' $((1<<$SPECCOPYNUM))`; /usr/bin/taskset $MYMASK $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command, using taskset, is used for Linux64 systems without numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:
submit= numactl --localalloc --physcpubind=$SPECCOPYNUM $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command is used for Linux64 systems with support for numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:

Shell, Environment, and Other Software Settings

numactl --interleave=all "runspec command"
Launching a process with numactl --interleave=all sets the memory interleave policy so that memory will be allocated using round robin on nodes. When memory cannot be allocated on the current interleave target fall back to other nodes.
KMP_STACKSIZE
Specify stack size to be allocated for each thread.
KMP_AFFINITY
Syntax: KMP_AFFINITY=[<modifier>,...]<type>[,<permute>][,<offset>]
The value for the environment variable KMP_AFFINITY affects how the threads from an auto-parallelized program are scheduled across processors.
It applies to binaries built with -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows).
modifier:
    granularity=fine Causes each OpenMP thread to be bound to a single thread context.
type:
    compact Specifying compact assigns the OpenMP thread <n>+1 to a free thread context as close as possible to the thread context where the <n> OpenMP thread was placed.
    scatter Specifying scatter distributes the threads as evenly as possible across the entire system.
permute: The permute specifier is an integer value controls which levels are most significant when sorting the machine topology map. A value for permute forces the mappings to make the specified number of most significant levels of the sort the least significant, and it inverts the order of significance.
offset: The offset specifier indicates the starting position for thread assignment.

Please see the Thread Affinity Interface article in the Intel Composer XE Documentation for more details.

Example: KMP_AFFINITY=granularity=fine,scatter
Specifying granularity=fine selects the finest granularity level and causes each OpenMP or auto-par thread to be bound to a single thread context.
This ensures that there is only one thread per core on cores supporting HyperThreading Technology
Specifying scatter distributes the threads as evenly as possible across the entire system.
Hence a combination of these two options, will spread the threads evenly across sockets, with one thread per physical core.

Example: KMP_AFFINITY=compact,1,0
Specifying compact will assign the n+1 thread to a free thread context as close as possible to thread n.
A default granularity=core is implied if no granularity is explicitly specified.
Specifying 1,0 sets permute and offset values of the thread assignment.
With a permute value of 1, thread n+1 is assigned to a consecutive core. With an offset of 0, the process's first thread 0 will be assigned to thread 0.
The same behavior is exhibited in a multisocket system.
OMP_NUM_THREADS
Sets the maximum number of threads to use for OpenMP* parallel regions if no other value is specified in the application. This environment variable applies to both -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores: export OMP_NUM_THREADS=8
Set stack size to unlimited
The command "ulimit -s unlimited" is used to set the stack size limit to unlimited.
Free the file system page cache
The command "echo 3> /proc/sys/vm/drop_caches" is used to free up the filesystem page cache as well as reclaimable slab objects like dentries and inodes.

Red Hat Specific features

Transparent Huge Pages
On RedHat EL 6 and later, Transparent Hugepages increase the memory page size from 4 kilobytes to 2 megabytes. Transparent Hugepages provide significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead.
Hugepages are used by default unless the /sys/kernel/mm/redhat_transparent_hugepage/enabled field is changed from its RedHat EL6 default of 'always'.

Operating System Tuning Parameters

Install only the relevant files

Select "minimal" mode when installing the operating system,so that many services are not installed,this will reduce the consumption of resources by the operating system itself. And then only install necessary files of cpu test by yum.

SCALING_GOVERNOR

Setting this environment variable to "performance" to enable cores to run at performance mode.

"scaling_governor" is a configuration file in Linux's "cpufreq" model. There are five mode in "scaling_governor" which are performance, powersave, userspace, ondemand, and conservative.

Performance: Lock the CPU's frequency at top speed without adjusting dynamically,which may require additional power;

Powersave: CPU will work at the minimum frequency;

Userspace: Provides the corresponding interface for the user-mode application program to adjust the frequency of CPU;

Ondemand: Quick dynamic adjustment of CPU frequency on demand, and will reach the maximum frequency;

Conservative: Frequency will be adjusted on demand.

We use "cpupower frequency-set -g performance" to set this environment variable to "performance".

tuned-adm

A commandline interface for switching between different tuning profiles available in supported Linux distributions. The distribution provided profiles are located in /usr/lib/tuned and the user defined profiles in /etc/tuned. To set a profile, one can issue the command "tuned-adm profile (profile_name)". Below are details about some relevant profiles.

tuned-adm command line utility allows user to switch between user definable tuning profiles.[active, profile (name), off]

throughput-performance: For typical throughput performance tuning. Disables power saving mechanisms and enables sysctl settings that improve the throughput performance of disk and network I/O. CPU governor is set to performance and CPU energy performance bias is set to performance. Disk readahead values are increased;

latency-performance: For low latency performance tuning. Disables power saving mechanisms. CPU governor is set to performance and locked to the low C states. CPU energy performance bias to performance;

balanced: Default profile provides balanced power saving and performance. It enables CPU and disk plugins of tuned and makes the conservative governor is active and also sets the CPU energy performance bias to normal. It also enables power saving on audio and graphics card;

powersave: Maximal power saving for whole system. It sets the CPU governor to ondemand governor and energy performance bias to powersave. It also enable power saving on USB, SATA, audio and graphics card;

We use "tuned-adm profiel throughput-performance" to set this environment variable to "throughput-performance".

HUGETLB_MORECORE

Setting this environment variable to "yes" to enable applications to use large pages.

LD_PRELOAD=/usr/lib64/libhugetlbfs.so

Setting this environment variable is necessary to enable applications to use large pages.

Firmware / BIOS / Microcode Settings

ENERGY_PERF_BIAS_CFG mode

This BIOS option allows for processor performance and power optmization. Available settings are:

Performance: High performance with less need for power saving.

Balanced Performance (Default Setting): Provides optimal performance efficiency.

Balanced Power: Provides optimal power efficiency.

Power: High power saving with less need for performance.

Hardware Prefetch:

This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm In some cases, setting this option to Disabled may improve performance.Users should only disable this option after performing application benchmarking to verify improved performance in their environment. Hardware Prefetching is typically accomplished by having a dedicated hardware mechanism in the processor that watches the stream of instructions or data being requested by the executing program, recognizes the next few elements that the program might need based on this stream and prefetches into the processor's cache. The default setting is Enable.

Intel Turbo boost Technology:

Enabling this option allows the processor cores to automatically increase its frequency and increasing performance if it is running below power, temperature.The default setting is Enable.

Intel Hyper Threading Technology:

Enabling this option allows to use processor resources more efficiently, enabling multiple threads to run on each core and increases processor throughput, improving overall performance on threaded software.The default setting is Enable.

Memory Frequency:

This BIOS setting allows the memory to be clocked to the highest supported frequency.

VT Support

If virtualization is not used, this option should be set to "Disabled", this can result in slight performance liftings and energy savings.The default setting is Enable.

C1E Support

Enabling this option, which is the default, allows the processor to transition to its minimum frequency when entering the power state C1. If the switch is disabled the CPU stays at its maximum frequency in C1. Because of the increase of power consumption users should only enable this option after performing application benchmarking to verify improved performance in their environment.

QPI Link Frequency Select

This switch allows the configuration of the QPI link speed. Default is auto, which configures the optimal link speed automatically.

IMC (Integrated memory controller) Interleaving

This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs), Memory could be interleaved across sockets, memory controllers, DDR channels, Ranks. Memory is interleaved for performance and thermal distribution.

If IMC Interleaving is set to 2-way, addresses will be interleaved between the two IMCs.

If IMC Interleaving is set to 1-way, there will be no interleaving.

If IMC Interleaving is set to auto, it depends on the SNC (Sub NUMA Clustering) setting, when SNC is set to enbaled, the IMC Interleaving will be 1-way interleave, SNC is set to disabled, the IMC Interleaving will be 2-way interleave.

If SNC is disabled, IMC Interleaving should be set to 2-way. If SNC is enabled, IMC Interleaving should be set to 1-way.

Sub NUMA Cluster (SNC)

Sub NUMA Clustering (SNC) is a feature for breaking up the LLC into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. It improves average latency to the LLC.

SNC2: supports 2-way clustering. Utilizes LLC capacity efficiently and reduces latency due to core/IMC proximity. This may provide performance improvement on NUMA-aware operating systems.

SNC4: supports 4-way clustering. Utilizes LLC capacity more efficiently and reduces latency due to core/IMC proximity. This may provide performance improvement on NUMA-aware operating systems.

disable: supports 1-cluster and 2-way IMC interleave, the LLC is treated as one cluster.

LLC Dead Line Allocation

In some Intel CPU caching schemes, mid-level cache (MLC) evictions are filled into the last level cache (LLC). If a line is evicted from the MLC to the LLC, the core can flag the evicted MLC lines as "dead". This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if the option is disabled.

Values for this BIOS option can be:

Disabled: Disabling this option can save space in the LLC by never filling MLC dead lines into the LLC.

Enabled: Opportunistically fill MLC dead lines in LLC, if space is available.

Last Level Cache (LLC)Prefetch

This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit (DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.

Values for this BIOS option can be:

Disabled: Disables the LLC prefetcher. The other core prefetchers are unaffected.

Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.

Xtended Prediction Table (XPT) Prefetch

The Xtended Prediction Table (XPT) prefetcher exists on top of other prefetchers that can prefetch data into the DCU, MLC, and LLC. The XPT prefetcher will issue a speculative DRAM read request in parallel to an LLC lookup. This prefetch bypasses the LLC, saving latency. In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.

Values for this BIOS option can be:

Enabled: Allows a read request sent to the LLC to speculatively issue a copy of the read to DRAM.

Disabled: Read requests to the LLC are not allowed to send a speculative read to DRAM.

Active Cores

The Avtive Cores allows you to choose how many Cores you want to enable for each CPU

Virtual Numa

Devide physical NUMA nodes into evenly sized virtual NUMA nodes in ACPI table. The default setting is Disabled.

Values for this BIOS option can be:

Enabled: Physical NUMA nodes will be devided into evenly sized virtual NUMA nodes.

Disabled: Physical NUMA nodes will not be devided into virtual NUMA nodes.

Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/Intel-ic2023-official-linux64.html,
http://www.spec.org/cpu2017/flags/Inspur-Platform-Settings-intel-V3.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/Intel-ic2023-official-linux64.xml,
http://www.spec.org/cpu2017/flags/Inspur-Platform-Settings-intel-V3.xml.

For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2023 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.1.9.
Report generated on 2023-05-09 16:01:34 by SPEC CPU2017 flags formatter v5178.