Base Compiler Invocation
C benchmarks
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- icx
![[user]](https://www.spec.org/auto/cpu2017/images/user.png)
- CC, LD
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Invoke the Intel oneAPI DPC++ C compiler.
C++ benchmarks
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- icpx
- CXX, LD
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Invoke the Intel oneAPI DPC++ C++ compiler.
Fortran benchmarks
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- ifort
- FC, LD
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Invoke the Intel Fortran compiler.
Copyright © 2016 Intel Corporation. All Rights Reserved.
Invoke the Intel oneAPI DPC++ C compiler.
Invoke the Intel oneAPI DPC++ C++ compiler.
Invoke the Intel Fortran compiler.
![[benchmark]](https://www.spec.org/auto/cpu2017/images/benchmark.png)
This macro specifies that the target system uses the LP64 data model; specifically, that integers are 32 bits, while longs and pointers are 64 bits.
This macro indicates that the benchmark is being compiled on an AMD64-compatible system running the Linux operating system.
![[suite]](https://www.spec.org/auto/cpu2017/images/suite.png)
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This flag can be set for SPEC compilation for LINUX using default compiler.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
Definition of this macro indicates that compilation for parallel operation is enabled, and that any OpenMP directives or pragmas will be visible to the compiler. The behavior of this macro is overridden if -DSPEC_SUPPRESS_OPENMP also appears in the list of compilation flags.
Sets the language dialect to conform to the indicated C standard.
Compiles for a 64-bit (LP64) data model.
Enable SmartHeap and/or other library usage by forcing the linker to ignore multiple definitions if present
Code is optimized for Intel(R) processors with support for CORE-AVX512 instructions. The resulting code may contain unconditional use of features that are not supported on other processors. This option also enables new optimizations in addition to Intel processor-specific optimizations including advanced data layout and code restructuring optimizations to improve memory accesses for Intel processors.
Do not use this option if you are executing a program on a processor that is not an Intel processor. If you use this option on a non-compatible processor to compile the main program (in Fortran) or the function main() in C/C++, the program will display a fatal run-time error if they are executed on unsupported processors.
Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:
On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.
Enable fast math mode. This option may yield faster code for programs that do not require the guarantees of exact implementation of IEEE or ISO rules/specifications for math functions.
Performs link time optimizations, which is also known as Interprocedural Optimizations.
Generate floating-point arithmetic for selected unit unit. Here use scalar floating-point instructions present in the SSE instruction set
Tells the compiler the maximum number of times to unroll loops. For example -funroll-loops0 would disable unrolling of loops.
Controls the level of memory layout transformations performed by the compiler. This option can improve cache reuse and cache locality.
This option instructs compiler to align branches and fused branches on 32 byte boundaries
Specify build time link path for jemalloc 64bit built to support the CPU 2017 build. See jemalloc.net for more information.
Linker toggle to specify jemalloc linker library. See jemalloc.net for more information.
Definition of this macro indicates that compilation for parallel operation is enabled, and that any OpenMP directives or pragmas will be visible to the compiler. The behavior of this macro is overridden if -DSPEC_SUPPRESS_OPENMP also appears in the list of compilation flags.
Compiles for a 64-bit (LP64) data model.
Enable SmartHeap and/or other library usage by forcing the linker to ignore multiple definitions if present
Code is optimized for Intel(R) processors with support for CORE-AVX512 instructions. The resulting code may contain unconditional use of features that are not supported on other processors. This option also enables new optimizations in addition to Intel processor-specific optimizations including advanced data layout and code restructuring optimizations to improve memory accesses for Intel processors.
Do not use this option if you are executing a program on a processor that is not an Intel processor. If you use this option on a non-compatible processor to compile the main program (in Fortran) or the function main() in C/C++, the program will display a fatal run-time error if they are executed on unsupported processors.
Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:
On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.
Enable fast math mode. This option may yield faster code for programs that do not require the guarantees of exact implementation of IEEE or ISO rules/specifications for math functions.
Performs link time optimizations, which is also known as Interprocedural Optimizations.
Generate floating-point arithmetic for selected unit unit. Here use scalar floating-point instructions present in the SSE instruction set
Tells the compiler the maximum number of times to unroll loops. For example -funroll-loops0 would disable unrolling of loops.
Controls the level of memory layout transformations performed by the compiler. This option can improve cache reuse and cache locality.
This option instructs compiler to align branches and fused branches on 32 byte boundaries
Build time link path for libraries supplied with the compiler (for example, the qkmalloc library).
Linker toggle to specify qkmalloc linker library. See https://software.intel.com/en-us/articles/intel-c-compiler-190-for-linux-release-notes-for-intel-parallel-studio-xe-2019#custalloc for more information.
Compiles for a 64-bit (LP64) data model.
Code is optimized for Intel(R) processors with support for CORE-AVX512 instructions. The resulting code may contain unconditional use of features that are not supported on other processors. This option also enables new optimizations in addition to Intel processor-specific optimizations including advanced data layout and code restructuring optimizations to improve memory accesses for Intel processors.
Do not use this option if you are executing a program on a processor that is not an Intel processor. If you use this option on a non-compatible processor to compile the main program (in Fortran) or the function main() in C/C++, the program will display a fatal run-time error if they are executed on unsupported processors.
Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:
On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
-no-prec-div enables optimizations that give slightly less precise results than full IEEE division.
When you specify -no-prec-div along with some optimizations, such as -xN and -xB (Linux) or /QxN and /QxB (Windows), the compiler may change floating-point division computations into multiplication by the reciprocal of the denominator. For example, A/B is computed as A * (1/B) to improve the speed of the computation.
However, sometimes the value produced by this transformation is not as accurate as full IEEE division. When it is important to have fully precise IEEE division, do not use -no-prec-div. This will enable the default -prec-div and the result will be more accurate, with some loss of performance.
Controls the level of memory layout transformations performed by the compiler. This option can improve cache reuse and cache locality.
Option standard-realloc-lhs (the default), tells the compiler that when the left-hand side of an assignment is an allocatable object, it should be reallocated to the shape of the right-hand side of the assignment before the assignment occurs. This is the current Fortran Standard definition. This feature may cause extra overhead at run time. This option has the same effect as option assume realloc_lhs.
If you specify nostandard-realloc-lhs, the compiler uses the old Fortran 2003 rules when interpreting assignment statements. The left-hand side is assumed to be allocated with the correct shape to hold the right-hand side. If it is not, incorrect behavior will occur. This option has the same effect as option assume norealloc_lhs.
The align toggle changes how data elements are aligned. Variables and arrays are analyzed and memory layout can be altered. Specifying array32byte will look for opportunities to transform and reailgn arrays to 32byte boundaries.
Make all local variables AUTOMATIC. Same as -automatic
This option instructs compiler to align branches and fused branches on 32 byte boundaries
This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.
Enable optimizations for speed. This is the generally recommended
optimization level. This option also enables:
- Inlining of intrinsics
- Intra-file interprocedural optimizations, which include:
- inlining
- constant propagation
- forward substitution
- routine attribute propagation
- variable address-taken analysis
- dead static function elimination
- removal of unreferenced variables
- The following capabilities for performance gain:
- constant propagation
- copy propagation
- dead-code elimination
- global register allocation
- global instruction scheduling and control speculation
- loop unrolling
- optimized code selection
- partial redundancy elimination
- strength reduction/induction variable simplification
- variable renaming
- exception handling optimizations
- tail recursions
- peephole optimizations
- structure assignment lowering and optimizations
- dead store elimination
Enable optimizations for speed and disables some optimizations that increase code size and affect speed.
To limit code size, this option:
The O1 option may improve performance for applications with very large code size, many branches, and execution time not dominated by code within loops.
-O1 sets the following options:Tells the compiler the maximum number of times to unroll loops. For example -funroll-loops0 would disable unrolling of loops.
-fno-builtin disables inline expansion for all intrinsic functions.
This option trades off floating-point precision for speed by removing the restriction to conform to the IEEE standard.
EBP is used as a general-purpose register in optimizations.
Places each function in its own COMDAT section.
Flushes denormal results to zero.
"cpupower frequency-set" provides a simplified mechanism to adjust processor frequencies when cpu frequency scaling is enabled in the OS. See the cpupower-frequency-set man page for details.Here is a brief description of options used in the config file. By default, settings are applied to all logical cpus in the system.Frequencies can be passed in Hz, kHz (default), MHz, GHz, or THz by postfixing the value with the desired unit name, without any space. Available frequencies and governors can be determined with "cpupower frequency-info".
Tmpfs is a file system which keeps all files in virtual memory.A tmpfs file system will go to swap if memory pressure demands real memory for applications. This can have a very negative effect on the I/O load and system performance
nohz_full: This kernel option sets adaptive tick mode (NOHZ_FULL) to specified porcessors. Since the number of interrupts is reduced to ones per second, latency-sensitive applications can take advantage of it.
This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.
Intel Turbo boost Technology, Enabling this option allows the processor cores to automatically increase its frequency and increasing performance if it is running below power, temperature.
Enabling this option allows to use processor resources more efficiently, enabling multiple threads to run on each core and increases processor throughput, improving overall performance on threaded software.
Values for this BIOS setting can be: Custom: Allows the user to setup all of the BIOS options according to their requirement. Performance: Maximize the performance of the server. Efficiency: Maximize the power efficiency of the server. Load Balance: The system's performance and power consumption will be adjusted automatically according to the loading.
Enable or disable reporting of the CPU C6 State (ACPI C3) to the OS.
When set to Enabled, the processor is allowed to switch to nimimum performance and save power when idle.
This option allows for correction of soft memory errors. Over the length of system runtime, the risk of producing multi-bit and uncorrected errors is reduced with this option. Values for this BIOS setting can be:
Enabled: Correction of soft memory errors can occur during runtime.
Disabled: Soft memory error correction is turned off during runtime.
This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs), Memory could be interleaved across sockets, memory controllers, DDR channels, Ranks. Memory is interleaved for performance and thermal distribution.
If IMC Interleaving is set to 2-way, addresses will be interleaved between the two IMCs.
If IMC Interleaving is set to 1-way, there will be no interleaving.
If IMC Interleaving is set to auto, it depends on the SNC (Sub NUMA Clustering) setting, when SNC is set to enbaled, the IMC Interleaving will be 1-way interleave, SNC is set to disabled, the IMC Interleaving will be 2-way interleave.
If SNC is disabled, IMC Interleaving should be set to 2-way. If SNC is enabled, IMC Interleaving should be set to 1-way.
SNC breaks up the last level cache (LLC) into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. SNC improves average latency to the LLC and memory. SNC is a replacement for the cluster on die (COD) feature found in previous processor families. For a multi-socketed system, all SNC clusters are mapped to unique NUMA (Non Uniform Memory Access) domains.
SNC AUTO supports 1-cluster or 2-clusters depending on IMC interleave. SNC and IMC interleave both AUTO will support 1-cluster 2-way IMC interleave.
SNC Enable supports Full SNC (2 clusters) and 1-way IMC interleave. Utilizes LLC capacity more efficiently and reduces latency due to core/IMC proximity. This may provide performance improvement on NUMA-aware operating systems.
SNC disable supports 1-cluster and 2-way IMC interleave, the LLC is treated as one cluster.
In some Intel CPU caching schemes, mid-level cache (MLC) evictions are filled into the last level cache (LLC). If a line is evicted from the MLC to the LLC, the core can flag the evicted MLC lines as "dead.” This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if the option is disabled.
Values for this BIOS option can be:
Disabled: Disabling this option can save space in the LLC by never filling MLC dead lines into the LLC.
Enabled: Opportunistically fill MLC dead lines in LLC, if space is available.
This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit (DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.
Values for this BIOS option can be:
Disabled: Disables the LLC prefetcher. The other core prefetchers are unaffected.
Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.
The Xtended Prediction Table (XPT) prefetcher exists on top of other prefetchers that can prefetch data into the DCU, MLC, and LLC. The XPT prefetcher will issue a speculative DRAM read request in parallel to an LLC lookup. This prefetch bypasses the LLC, saving latency. In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.
Values for this BIOS option can be:
Enabled: Allows a read request sent to the LLC to speculatively issue a copy of the read to DRAM.
Disabled: Read requests to the LLC are not allowed to send a speculative read to DRAM.
Adaptive Double Device Data Correction (ADDDC), which is an enhanced feature to DDDC. This function is used to correct data errors on two memory particles, ADDDC still has single-particle multi-bit error correction capability after the first particle failure occurs and is replaced.
Values for this BIOS option can be:
Enabled: Enable the ADDDC Sparing function.
Disabled: Disable the ADDDC Sparing function.
Flag description origin markings:
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Indicates that the flag description came from the user flags file. |
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Indicates that the flag description came from the suite-wide flags file. |
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Indicates that the flag description came from a per-benchmark flags file. |
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2022 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.1.0.
Report generated on 2022-06-07 15:48:43 by SPEC CPU2017 flags formatter v5178.