CPU2017 Flag Description
Supermicro A+ Server 2124GQ-NART (H12DDG-Q-CPU6 , AMD EPYC 7713)
Compilers: AMD Optimizing C/C++ Compiler Suite
Base Compiler Invocation
-
- clang
![[user]](https://www.spec.org/auto/cpu2017/images/user.png)
- CC, LD
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang++
- CXX, LD
-
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- flang
- FC, LD
-
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on
which high-level mode setting is passed, Flang will stop before doing a full link.
Peak Compiler Invocation
-
- clang
- CC, LD
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang++
- CXX, LD
-
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- flang
- FC, LD
-
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on
which high-level mode setting is passed, Flang will stop before doing a full link.
Base Portability Flags
-
![[suite]](https://www.spec.org/auto/cpu2017/images/suite.png)
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
Peak Portability Flags
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
Base Optimization Flags
-
- -m64
- CC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -O3
- COPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -ffast-math
- COPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -march=znver3
- COPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -fstruct-layout=5
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- -m64
- CXX, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -O3
- CXXOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -ffast-math
- CXXOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -march=znver3
- CXXOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
-
-
-
-
-
-
- -mllvm -aggressive-loop-unswitch
- CXXOPTIMIZE
-
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch)
based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be
minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based
on the number of times they are used within the loop. The heuristic can be controlled with the following options:
- -unswitch-identical-branches-min-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n>
where n is a positive integer and lower value of <n> facilitates more unswitching
- -unswitch-identical-branches-max-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n>
where n is a positive integer and higher value of <n> facilitates more unswitching
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads
to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer
compilation times.
- Includes:
-
-
-
-
-
-
-
-
-
-
-
-
-
- -m64
- FC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
-
- -O3
- FOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -ffast-math
- FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -march=znver3
- FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
-
-
-
-
-
-
Peak Optimization Flags
-
- -m64
- CC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
-
-
- -march=znver3
- COPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -fstruct-layout=7
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
-
-
- -m32
- CC, LD
-
Generate code for a 32-bit environment. The 32-bit environment sets int, long and
pointer to 32 bits and generates code that runs on any i386 system. The compiler generates x86 or IA32
32-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
- -march=znver3
- COPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -fstruct-layout=7
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
- EXTRA_COPTIMIZE
-
In the 502/602.gcc benchmark description,
"multiple definitions of symbols" is listed under the "Known Portability Issues" section, and this option is one of the
suggested workarounds. This option causes Clang to revert to the same inlining behavior that GCC does when in pre-C99
mode.
-
-
- -m64
- CC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -march=znver3
- COPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -fstruct-layout=7
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
-
-
- -m32
- CXX, LD
-
Generate code for a 32-bit environment. The 32-bit environment sets int, long and
pointer to 32 bits and generates code that runs on any i386 system. The compiler generates x86 or IA32
32-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
- -march=znver3
- CXXOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
-
-
-
-
-
- -mllvm -aggressive-loop-unswitch
- CXXOPTIMIZE
-
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch)
based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be
minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based
on the number of times they are used within the loop. The heuristic can be controlled with the following options:
- -unswitch-identical-branches-min-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n>
where n is a positive integer and lower value of <n> facilitates more unswitching
- -unswitch-identical-branches-max-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n>
where n is a positive integer and higher value of <n> facilitates more unswitching
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads
to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer
compilation times.
- Includes:
-
-
-
- EXTRA_CXXFLAGS
-
Block Reordering
Possible values:
- none: No block reorder
- simple: Simple block reorder
- aggressive: Aggressive block reorder
-
-
-
-
- -m64
- CXX, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -march=znver3
- CXXOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
-
-
-
-
-
- -mllvm -aggressive-loop-unswitch
- CXXOPTIMIZE
-
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch)
based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be
minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based
on the number of times they are used within the loop. The heuristic can be controlled with the following options:
- -unswitch-identical-branches-min-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n>
where n is a positive integer and lower value of <n> facilitates more unswitching
- -unswitch-identical-branches-max-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n>
where n is a positive integer and higher value of <n> facilitates more unswitching
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads
to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer
compilation times.
- Includes:
-
-
-
- EXTRA_CXXFLAGS
-
Block Reordering
Possible values:
- none: No block reorder
- simple: Simple block reorder
- aggressive: Aggressive block reorder
-
-
-
-
Implicitly Included Flags
This section contains descriptions of flags that were included implicitly
by other flags, but which do not have a permanent home at SPEC.
-
- -O2
-
Moderate level of optimization which enables most optimizations. This is the default when no "-O" option is
specified, or if no value is specified (i.e. "-O").
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -O1
-
Somewhere between -O0 and -O2.
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
-
-
- -O3
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
Using numactl to bind processes and memory to cores
For multi-copy runs or single copy runs on systems with multiple sockets, it is advantageous to bind a process to a
particular core. Otherwise, the OS may arbitrarily move your process from one core to another. This can affect
performance. To help, SPEC allows the use of a "submit" command where users can specify a utility to use to bind
processes. We have found the utility 'numactl' to be the best choice.
numactl runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a
command and inherited by all of its children. The numactl flag "--physcpubind" specifies
which core(s) to bind the process. "-l" instructs numactl to keep a process's memory on the
local node while "-m" specifies which node(s) to place a process's memory. For full details on using
numactl, please refer to your Linux documentation, 'man numactl'
Note that some older versions of numactl incorrectly interpret application arguments as its own. For
example, with the command "numactl --physcpubind=0 -l a.out -m a", numactl will interpret
a.out's "-m" option as its own "-m" option. To work around this problem, we put
the command to be run in a shell script and then run the shell script using numactl. For example:
"echo 'a.out -m a' > run.sh ; numactl --physcpubind=0 bash run.sh"
Transparent Huge Pages (THP)
THP is an abstraction layer that automates most aspects of creating, managing, and using huge pages. THP is designed
to hide much of the complexity in using huge pages from system administrators and developers, as normal huge pages
must be assigned at boot time, can be difficult to manage manually, and often require significant changes to code in
order to be used effectively. Most recent Linux OS releases have THP enabled by default.
ulimit -s <n>
Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.
ulimit -l <n>
Sets the maximum size of memory that may be locked into physical memory.
powersave -f (on SuSE)
Makes the powersave daemon set the CPUs to the highest supported frequency.
/etc/init.d/cpuspeed stop (on Red Hat)
Disables the cpu frequency scaling program in order to set the CPUs to the highest supported frequency.
LD_LIBRARY_PATH
An environment variable that indicates the location in the filesystem of bundled libraries to use when running the
benchmark binaries.
kernel/randomize_va_space
This option can be used to select the type of process address space randomization that is used in the system, for
architectures that support this feature.
- 0 - Turn the process address space randomization off. This is the default for architectures that do not support
this feature anyway, and kernels that are booted with the "
norandmaps" parameter.
- 1 - Make the addresses of mmap base, stack and VDSO page randomized. This, among other things, implies that
shared libraries will be loaded to random addresses. Also for PIE-linked binaries, the location of code start is
randomized. This is the default if the
CONFIG_COMPAT_BRK option is enabled.
- 2 - Additionally enable heap randomization. This is the default if
CONFIG_COMPAT_BRK is
disabled.
MALLOC_CONF
An environment variable set to tune the jemalloc allocation strategy during the execution of the binaries. This
environment variable setting is not needed when building the binaries on the system under test.
PGHPF_ZMEM
An environment variable used to initialize the allocated memory. Setting PGHPF_ZMEM to "Yes" has the effect of
initializing all allocated memory to zero.
GOMP_CPU_AFFINITY
This environment variable is used to set the thread affinity for threads spawned by OpenMP.
OMP_DYNAMIC
This environment variable is defined as part of the OpenMP standard.
Setting it to "false" prevents the OpenMP runtime from dynamically adjusting the number of threads to use for parallel
execution.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
OMP_SCHEDULE
This environment variable is defined as part of the OpenMP standard.
Setting it to "static" causes loop iterations to be assigned to threads in round-robin fashion in the order of the thread
number.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
OMP_STACKSIZE
This environment variable is defined as part of the OpenMP standard and controls the size of the stack for threads created
by OpenMP.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
OMP_THREAD_LIMIT
This environment variable is defined as part of the OpenMP standard and limits the maximum number of OpenMP threads that
can be created.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
- kernel.randomize_va_space (ASLR)
-
This setting can be used to select the type of process address space randomization.
Defaults differ based on whether the architecture supports ASLR, whether the kernel
was built with the CONFIG_COMPAT_BRK option or not, or the kernel boot options used.
Possible settings:
- 0: Turn process address space randomization off.
- 1: Randomize addresses of mmap base, stack, and VDSO pages.
- 2: Additionally randomize the heap. (This is probably the default.)
Disabling ASLR can make process execution more deterministic and runtimes more consistent.
For more information see the randomize_va_space entry in the
Linux sysctl documentation.
- Transparent Hugepages (THP)
-
THP is an abstraction layer that automates most aspects of creating, managing,
and using huge pages. It is designed to hide much of the complexity in using
huge pages from system administrators and developers. Huge pages
increase the memory page size from 4 kilobytes to 2 megabytes. This provides
significant performance advantages on systems with highly contended resources
and large memory workloads. If memory utilization is too high or memory is badly
fragmented which prevents hugepages being allocated, the kernel will assign
smaller 4k pages instead. Most recent Linux OS releases have THP enabled by default.
THP usage is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/enabled.
Possible values:
- never: entirely disable THP usage.
- madvise: enable THP usage only inside regions marked MADV_HUGEPAGE using madvise(3).
- always: enable THP usage system-wide. This is the default.
THP creation is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/defrag.
Possible values:
- never: if no THP are available to satisfy a request, do not attempt to make any.
- defer: an allocation requesting THP when none are available get normal pages while requesting THP creation in the background.
- defer+madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3); for all other regions it's like "defer".
- madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3). This is the default.
- always: an allocation requesting THP when none are available will stall until some are made.
An application that "always" requests THP often can benefit from waiting for an allocation until those huge pages can be assembled.
For more information see the Linux transparent hugepage documentation.
- Determinism Control:
-
This BIOS option allows for choose AGESA determinism control.
AGESA is an acronym for "AMD Generic Encapsulated Software Architecture."
AGESA is a bootstrap protocol by which system devices on AMD64-architecture mainboards are initialized, it responsible for the initialization of the processor cores, memory, and the HyperTransport controller.
Available settings are:
- Manual: User can customize determinism slider.
- Auto (Default setting): Use the processor fused determinism control.
- Determinism Slider:
-
This BIOS option allows for Enable/Disable AGESA determinism to control performance.
AGESA is an acronym for "AMD Generic Encapsulated Software Architecture."
AGESA is a bootstrap protocol by which system devices on AMD64-architecture mainboards are initialized, it responsible for the initialization of the processor cores, memory, and the HyperTransport controller.
Available settings are:
- Performance: AGESA will enable 100% deterministic performance control.
- Power: AGESA will not enable deterministic performance control.
- Auto (Default setting): Use default value for deterministic performance control.
- cTDP Control:
-
This BIOS option is for "Configurable TDP (cTDP)", it allows user can set customized value for TDP. Available settings are:
- Auto (Default setting): Use the fused TDP value.
- Manual: Let user specifies customized TDP value.
- cTDP:
-
TDP is an acronym for “Thermal Design Power.” TDP is the recommended target for power used when designing the cooling capacity for a server.
EPYC processors are able to control this target power consumption within certain limits. This capability is referred to as “configurable TDP” or "cTDP."
cTDP can be used to reduce power consumption for greater efficiency, or in some cases, increase power consumption above the default value to provide additional performance.
cTDP is controlled using a BIOS option.
The default EPYC cTDP value corresponds with the microprocessor’s nominal TDP. For the EPYC 7702, the default value is 200W.
The default cTDP value is set at a good balance between performance and energy efficiency.
The EPYC 7702 cTDP can be reduced as low as 180W, which will minimize the power consumption for the processor under load, but at the expense of peak performance.
Increasing the EPYC 7742 cTDP to 240W will maximize peak performance by allowing the CPU to maintain higher dynamic clock speeds, but will make the microprocessor less energy efficient.
Note that at maximum cTDP, the CPU thermal solution must be capable of dissipating at least 240W or the EPYC 7742 processor might engage in thermal throttling under load.
The available cTDP ranges for each EPYC model are in the table below:
| Model | Nominal TDP | Minimum cTDP | Maximum cTDP** |
|---|
| EPYC 7763 | 280W | 225W | 280W |
|---|
| EPYC 7713 | 225W | 225W | 240W |
|---|
| EPYC 7H12 | 280W | 225W | 280W |
|---|
| EPYC 7742 | 225W | 225W | 240W |
|---|
| EPYC 7702 | 200W | 165W | 200W |
|---|
| EPYC 7702P | 200W | 165W | 200W |
|---|
| EPYC 7662 | 240W | 225W | 240W |
|---|
| EPYC 7642 | 240W | 225W | 240W |
|---|
| EPYC 7552 | 200W | 165W | 200W |
|---|
| EPYC 7542 | 225W | 225W | 240W |
|---|
| EPYC 7532 | 200W | 165W | 200W |
|---|
| EPYC 7502 | 180W | 165W | 200W |
|---|
| EPYC 7502P | 180W | 165W | 200W |
|---|
| EPYC 7452 | 155W | 155W | 180W |
|---|
| EPYC 7F72 | 240W | 225W | 240W |
|---|
| EPYC 7402 | 180W | 165W | 200W |
|---|
| EPYC 7402P | 180W | 165W | 200W |
|---|
| EPYC 7352 | 155W | 155W | 180W |
|---|
| EPYC 7F52 | 240W | 225W | 240W |
|---|
| EPYC 7302 | 155W | 155W | 180W |
|---|
| EPYC 7302P | 155W | 155W | 180W |
|---|
| EPYC 7282 | 120W | 120W | 150W |
|---|
| EPYC 7272 | 120W | 120W | 150W |
|---|
| EPYC 7F32 | 180W | 165W | 200W |
|---|
| EPYC 7262 | 155W | 155W | 180W |
|---|
| EPYC 7252 | 120W | 120W | 150W |
|---|
| EPYC 7232P | 120W | 120W | 150W |
|---|
| EPYC 7601 | 180W | 165W | 200W |
|---|
| EPYC 7551 | 180W | 165W | 200W |
|---|
| EPYC 7501 | 155/170W | 135W | 155/170W* |
|---|
| EPYC 7451 | 180W | 165W | 200W |
|---|
| EPYC 7401 | 155/170W | 135W | 155/170W* |
|---|
| EPYC 7351 | 155/170W | 135W | 155/170W* |
|---|
| EPYC 7301 | 155/170W | 135W | 155/170W* |
|---|
| EPYC 7281 | 155/170W | 135W | 155/170W* |
|---|
| EPYC 7251 | 120W | 105W | 120W |
|---|
*Max TDP is 170W when DDR4 is operating at 2667 MT/sec, or 155W when DDR4 is operating at lower frequencies.
** cTDP must remain below the thermal solution design parameters or thermal throttling could be frequently encountered.
- IOMMU:
-
The I/O Memory Management Unit (IOMMU) extends the AMD64 system architecture by adding support for address translation and system memory access protection on DMA transfers from periph-eral devices.
IOMMU also helps filter and remap interrupts from peripheral devices.
Available settings are:
- Disabled: Disable IOMMU support.
- Enabled: Enable IOMMU support.
- Auto (Default setting): Use default value for IOMMU. The default value is disable.
- Package Power Limit Control:
-
This is a per processor Package Power Limit (PPT) value applicable for all populated processors in the system.
This can be set to limit the PPT to a certain value.
Available settings are:
- Auto (Default setting): Use the fused processor PPT value.
- Manual: Let user specifies customized processor PPT value.
- Package Power Limit:
-
Set customize processor Package Power Limit (PPT) value to be used on all populated processors in the system.
If set to 240 = Use the 240W PPT ***PPT will be used as the ASIC power limit***
- APBDIS:
-
APBDis is an IO Boost disable on uncore.
For any system user that needs to block these uncore optimizations that are impacting base core clock speed, we are exposing a method to disable this behavior called APBDis.
This locks the fabric clock to the non-boosted speeds.
Available settings are:
- 0: Disable APBDIS, locks the fabric clock to the non-boosted speeds.
- 1: Enable APBDIS, unlocks the fabric clock to the boosted speeds.
- Auto (Default setting): Use default value for APBDIS. The default value is 0.
- NUMA Nodes Per Socket:
-
Specifies the number of desired NUMA nodes per socket.
This option allows the user to divide the memory that each socket has into a certain number of NUMA memory nodes for optimal memory bandwidth.
Available settings are:
- NPS0: It will attempt to interleave the two sockets together.
- NPS1: Each processor socket will have one NUMA memory node.
- NPS2: Each processor socket will have two NUMA memory nodes.
- NPS4: Each processor socket will have four NUMA memory nodes.
- Auto (Default setting): Use default value for NUMA nodes per socket. The default value is NPS1.
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2021 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.1.0.
Report generated on 2021-03-30 15:32:45 by SPEC CPU2017 flags formatter v5178.
![[benchmark]](https://www.spec.org/auto/cpu2017/images/benchmark.png)