Base Compiler Invocation
C benchmarks
-
- icc
![[user]](https://www.spec.org/auto/cpu2017/images/user.png)
- CC, LD
-
Invoke the Intel C compiler.
C++ benchmarks
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- icpc
- CXX, LD
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Invoke the Intel C++ compiler.
Fortran benchmarks
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- ifort
- FC, LD
-
Invoke the Intel Fortran compiler.
Copyright © 2016 Intel Corporation. All Rights Reserved.
Invoke the Intel C compiler.
Invoke the Intel C++ compiler.
Invoke the Intel Fortran compiler.
Invoke the Intel C compiler.
Invoke the Intel C++ compiler.
Invoke the Intel Fortran compiler.
![[benchmark]](https://www.spec.org/auto/cpu2017/images/benchmark.png)
This macro specifies that the target system uses the LP64 data model; specifically, that integers are 32 bits, while longs and pointers are 64 bits.
This macro indicates that the benchmark is being compiled on an AMD64-compatible system running the Linux operating system.
![[suite]](https://www.spec.org/auto/cpu2017/images/suite.png)
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This flag can be set for SPEC compilation for LINUX using default compiler.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This macro specifies that the target system uses the LP64 data model; specifically, that integers are 32 bits, while longs and pointers are 64 bits.
This macro indicates that the benchmark is being compiled on an AMD64-compatible system running the Linux operating system.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This flag can be set for SPEC compilation for LINUX using default compiler.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
Some portability flags were found in optimization variables.
Compiles for a 64-bit (LP64) data model.
Invoke Intel C++ compiler next generation code generator.
Sets the language dialect to conform to the indicated C standard.
This option instructs compiler to align branches and fused branches on 32 byte boundaries
Enable SmartHeap and/or other library usage by forcing the linker to ignore multiple definitions if present
Code is optimized for Intel(R) processors with support for AVX2 instructions. The resulting code may contain unconditional use of features that are not supported on other processors. This option also enables new optimizations in addition to Intel processor-specific optimizations including advanced data layout and code restructuring optimizations to improve memory accesses for Intel processors.
Do not use this option if you are executing a program on a processor that is not an Intel processor. If you use this option on a non-compatible processor to compile the main program (in Fortran) or the function main() in C/C++, the program will display a fatal run-time error if they are executed on unsupported processors.
Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:
On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.
Enable fast math mode. This option may yield faster code for programs that do not require the guarantees of exact implementation of IEEE or ISO rules/specifications for math functions.
Performs link time optimizations, which is also known as Interprocedural Optimizations.
Generate floating-point arithmetic for selected unit unit. Here use scalar floating-point instructions present in the SSE instruction set
Tells the compiler the maximum number of times to unroll loops. For example -funroll-loops0 would disable unrolling of loops.
Instructs the compiler to use the GNU gold linker (gold) instead of the system linker when linking object files.
Controls the level of memory layout transformations performed by the compiler. This option can improve cache reuse and cache locality.
Definition of this macro indicates that compilation for parallel operation is enabled, and that any OpenMP directives or pragmas will be visible to the compiler. The behavior of this macro is overridden if -DSPEC_SUPPRESS_OPENMP also appears in the list of compilation flags.
Specify build time link path for jemalloc 64bit built to support the CPU 2017 build. See jemalloc.net for more information.
Linker toggle to specify jemalloc linker library. See jemalloc.net for more information.
Compiles for a 64-bit (LP64) data model.
Invoke Intel C++ compiler next generation code generator.
This option instructs compiler to align branches and fused branches on 32 byte boundaries
Enable SmartHeap and/or other library usage by forcing the linker to ignore multiple definitions if present
Code is optimized for Intel(R) processors with support for AVX2 instructions. The resulting code may contain unconditional use of features that are not supported on other processors. This option also enables new optimizations in addition to Intel processor-specific optimizations including advanced data layout and code restructuring optimizations to improve memory accesses for Intel processors.
Do not use this option if you are executing a program on a processor that is not an Intel processor. If you use this option on a non-compatible processor to compile the main program (in Fortran) or the function main() in C/C++, the program will display a fatal run-time error if they are executed on unsupported processors.
Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:
On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.
Enable fast math mode. This option may yield faster code for programs that do not require the guarantees of exact implementation of IEEE or ISO rules/specifications for math functions.
Performs link time optimizations, which is also known as Interprocedural Optimizations.
Generate floating-point arithmetic for selected unit unit. Here use scalar floating-point instructions present in the SSE instruction set
Tells the compiler the maximum number of times to unroll loops. For example -funroll-loops0 would disable unrolling of loops.
Instructs the compiler to use the GNU gold linker (gold) instead of the system linker when linking object files.
Controls the level of memory layout transformations performed by the compiler. This option can improve cache reuse and cache locality.
Build time link path for libraries supplied with the compiler (for example, the qkmalloc library).
Linker toggle to specify qkmalloc linker library. See https://software.intel.com/en-us/articles/intel-c-compiler-190-for-linux-release-notes-for-intel-parallel-studio-xe-2019#custalloc for more information.
Compiles for a 64-bit (LP64) data model.
This option instructs compiler to align branches and fused branches on 32 byte boundaries
Code is optimized for Intel(R) processors with support for AVX2 instructions. The resulting code may contain unconditional use of features that are not supported on other processors. This option also enables new optimizations in addition to Intel processor-specific optimizations including advanced data layout and code restructuring optimizations to improve memory accesses for Intel processors.
Do not use this option if you are executing a program on a processor that is not an Intel processor. If you use this option on a non-compatible processor to compile the main program (in Fortran) or the function main() in C/C++, the program will display a fatal run-time error if they are executed on unsupported processors.
Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:
On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
-no-prec-div enables optimizations that give slightly less precise results than full IEEE division.
When you specify -no-prec-div along with some optimizations, such as -xN and -xB (Linux) or /QxN and /QxB (Windows), the compiler may change floating-point division computations into multiplication by the reciprocal of the denominator. For example, A/B is computed as A * (1/B) to improve the speed of the computation.
However, sometimes the value produced by this transformation is not as accurate as full IEEE division. When it is important to have fully precise IEEE division, do not use -no-prec-div. This will enable the default -prec-div and the result will be more accurate, with some loss of performance.
Controls the level of memory layout transformations performed by the compiler. This option can improve cache reuse and cache locality.
Option standard-realloc-lhs (the default), tells the compiler that when the left-hand side of an assignment is an allocatable object, it should be reallocated to the shape of the right-hand side of the assignment before the assignment occurs. This is the current Fortran Standard definition. This feature may cause extra overhead at run time. This option has the same effect as option assume realloc_lhs.
If you specify nostandard-realloc-lhs, the compiler uses the old Fortran 2003 rules when interpreting assignment statements. The left-hand side is assumed to be allocated with the correct shape to hold the right-hand side. If it is not, incorrect behavior will occur. This option has the same effect as option assume norealloc_lhs.
The align toggle changes how data elements are aligned. Variables and arrays are analyzed and memory layout can be altered. Specifying array32byte will look for opportunities to transform and reailgn arrays to 32byte boundaries.
This option instructs compiler to align branches and fused branches on 32 byte boundaries
Enable SmartHeap and/or other library usage by forcing the linker to ignore multiple definitions if present
Instrument program for profiling for the first phase of two-phase profile guided otimization. This instrumentation gathers information about a program's execution paths and data values but does not gather information from hardware performance counters. The profile instrumentation also gathers data for optimizations which are unique to profile-feedback optimization.
-profgen:threadsafe option collects profile guided optimization data with guards for threaded applications.
Instructs the compiler to produce a profile-optimized
executable and merges available dynamic information (.dyn)
files into a pgopti.dpi file. If you perform multiple
executions of the instrumented program, -prof-use merges
the dynamic information files again and overwrites the
previous pgopti.dpi file.
Without any other options, the current directory is
searched for .dyn files
Code is optimized for Intel(R) processors with support for AVX2 instructions. The resulting code may contain unconditional use of features that are not supported on other processors. This option also enables new optimizations in addition to Intel processor-specific optimizations including advanced data layout and code restructuring optimizations to improve memory accesses for Intel processors.
Do not use this option if you are executing a program on a processor that is not an Intel processor. If you use this option on a non-compatible processor to compile the main program (in Fortran) or the function main() in C/C++, the program will display a fatal run-time error if they are executed on unsupported processors.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:
On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.
-no-prec-div enables optimizations that give slightly less precise results than full IEEE division.
When you specify -no-prec-div along with some optimizations, such as -xN and -xB (Linux) or /QxN and /QxB (Windows), the compiler may change floating-point division computations into multiplication by the reciprocal of the denominator. For example, A/B is computed as A * (1/B) to improve the speed of the computation.
However, sometimes the value produced by this transformation is not as accurate as full IEEE division. When it is important to have fully precise IEEE division, do not use -no-prec-div. This will enable the default -prec-div and the result will be more accurate, with some loss of performance.
Controls the level of memory layout transformations performed by the compiler. This option can improve cache reuse and cache locality.
Tells the compiler to remove the assumption that source code follows c99 signed overflow rules.
This option instructs compiler to align branches and fused branches on 32 byte boundaries
Specify build time link path for jemalloc 64bit built to support the CPU 2017 build. See jemalloc.net for more information.
Linker toggle to specify jemalloc linker library. See jemalloc.net for more information.
Compiles for a 64-bit (LP64) data model.
Invoke Intel C++ compiler next generation code generator.
Sets the language dialect to conform to the indicated C standard.
Instructs the compiler to use the GNU gold linker (gold) instead of the system linker when linking object files.
This option instructs compiler to align branches and fused branches on 32 byte boundaries
Enable SmartHeap and/or other library usage by forcing the linker to ignore multiple definitions if present
Instrument program for profiling for the first phase of two-phase profile guided otimization. This instrumentation gathers information about a program's execution paths and data values but does not gather information from hardware performance counters. The profile instrumentation also gathers data for optimizations which are unique to profile-feedback optimization.
Instructs the compiler to produce a profile-optimized executable and merges available dynamic information.
Code is optimized for Intel(R) processors with support for AVX2 instructions. The resulting code may contain unconditional use of features that are not supported on other processors. This option also enables new optimizations in addition to Intel processor-specific optimizations including advanced data layout and code restructuring optimizations to improve memory accesses for Intel processors.
Do not use this option if you are executing a program on a processor that is not an Intel processor. If you use this option on a non-compatible processor to compile the main program (in Fortran) or the function main() in C/C++, the program will display a fatal run-time error if they are executed on unsupported processors.
Performs link time optimizations, which is also known as Interprocedural Optimizations.
Enable O3 optimizations plus more aggressive optimizations, such as -ffinite-math-only –no-prec-div
Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:
On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.
Enable fast math mode. This option may yield faster code for programs that do not require the guarantees of exact implementation of IEEE or ISO rules/specifications for math functions.
Controls the level of memory layout transformations performed by the compiler. This option can improve cache reuse and cache locality.
Specify build time link path for jemalloc 64bit built to support the CPU 2017 build. See jemalloc.net for more information.
Linker toggle to specify jemalloc linker library. See jemalloc.net for more information.
Compiles for a 64-bit (LP64) data model.
Invoke Intel C++ compiler next generation code generator.
Sets the language dialect to conform to the indicated C standard.
This option instructs compiler to align branches and fused branches on 32 byte boundaries
Enable SmartHeap and/or other library usage by forcing the linker to ignore multiple definitions if present
Code is optimized for Intel(R) processors with support for AVX2 instructions. The resulting code may contain unconditional use of features that are not supported on other processors. This option also enables new optimizations in addition to Intel processor-specific optimizations including advanced data layout and code restructuring optimizations to improve memory accesses for Intel processors.
Do not use this option if you are executing a program on a processor that is not an Intel processor. If you use this option on a non-compatible processor to compile the main program (in Fortran) or the function main() in C/C++, the program will display a fatal run-time error if they are executed on unsupported processors.
Performs link time optimizations, which is also known as Interprocedural Optimizations.
Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:
On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.
Enable fast math mode. This option may yield faster code for programs that do not require the guarantees of exact implementation of IEEE or ISO rules/specifications for math functions.
Instructs the compiler to use the GNU gold linker (gold) instead of the system linker when linking object files.
Controls the level of memory layout transformations performed by the compiler. This option can improve cache reuse and cache locality.
This options tells the compiler to assume no aliasing in the program.
Specify build time link path for jemalloc 64bit built to support the CPU 2017 build. See jemalloc.net for more information.
Linker toggle to specify jemalloc linker library. See jemalloc.net for more information.
This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.
Enable optimizations for speed. This is the generally recommended
optimization level. This option also enables:
- Inlining of intrinsics
- Intra-file interprocedural optimizations, which include:
- inlining
- constant propagation
- forward substitution
- routine attribute propagation
- variable address-taken analysis
- dead static function elimination
- removal of unreferenced variables
- The following capabilities for performance gain:
- constant propagation
- copy propagation
- dead-code elimination
- global register allocation
- global instruction scheduling and control speculation
- loop unrolling
- optimized code selection
- partial redundancy elimination
- strength reduction/induction variable simplification
- variable renaming
- exception handling optimizations
- tail recursions
- peephole optimizations
- structure assignment lowering and optimizations
- dead store elimination
Enable optimizations for speed and disables some optimizations that increase code size and affect speed.
To limit code size, this option:
The O1 option may improve performance for applications with very large code size, many branches, and execution time not dominated by code within loops.
-O1 sets the following options:Tells the compiler the maximum number of times to unroll loops. For example -funroll-loops0 would disable unrolling of loops.
-fno-builtin disables inline expansion for all intrinsic functions.
This option trades off floating-point precision for speed by removing the restriction to conform to the IEEE standard.
EBP is used as a general-purpose register in optimizations.
Places each function in its own COMDAT section.
Flushes denormal results to zero.
Enable O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enable optimizations for maximum speed, such as:
On IA-32 and Intel EM64T processors, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times. The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations. The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.
C States:
C States allow the processor to enter lower power states when idle. When set to Enabled (OS controlled) or when set to Autonomous (if Hardware controlled is supported), the processor can operate in all available Power States to save power, but my increase memory latency and frequency jitter.
L3 cache as NUMA Domain:
This field specifies that each CCX within the processor will be declared as a NUMA Domain.
L1 Stream HW prefetcher, L2 Stream HW prefetcher:
Most workloads will benefit from the L1 and L2 Stream Hardware prefetchers gathering data and keeping the core pipeline busy. There are however some workloads that are very random in nature and will actually obtain better overall performance by disabling one or both of the prefetchers.
UPI Prefetch:
Enables you to get the memory read started early on DDR bus. The Ultra Path Interconnect (UPI) Rx path will spawn the speculative memory read to Integrated Memory Controller (iMC) directly.
Dynamic Link Width Management (DLWM):
DLWM reduces the XGMI link width between sockets from x16 to x8 (default), when no traffic is detected on the link. This feature is optimized to trade power between core and high IO/memory bandwidth workloads.
Forced = Force link width to x16, x8, or x2.
Forced = Force link width to x16, x8, or x2.
LLC Prefetch:
This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit (DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance. Disabled: Disables the LLC prefetcher. Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.
Dead Line LLC Alloc:
In the Skylake cache scheme, mid-level cache (MLC) evictions are filled into the last level cache (LLC). If a line is evicted from the MLC to the LLC, the Skylake core can flag the evicted MLC lines as "dead". This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if the option is disabled. Disabled: Disabling this option can save space in the LLC by never filling dead lines into the LLC. Enabled: Opportunistically fill dead lines in LLC, if space is available.
Directory AtoS:
AtoS optimization reduces remote read latencies for repeat read accesses without intervening writes.
Algorithm performance Boost Disable (ApbDis):
When enabled a specific hard-fused Data Fabric (SOC) p-state is forced for optimizing workloads sensitive to latency or throughput. When disabled P-states will be automatically managed by the Application Power Management, allowing the processor to provide maximum performance while remaining within a specified power-delivery and thermal envelope.
Fan Speed:
Selecting this option allows additional cooling to the server. In case hardware is added (example, new PCIe cards), it may require additional cooling. A fan speed offset causes fan speeds to increase (by the offset % value) over baseline fan speeds calculated by the Thermal Control algorithm. Maximum — Drives fan speeds to full speed.
Determinism Slider:
It controls whether BIOS will enable determinism to control performance. Performance: BIOS will enable 100% deterministic performance control. Power: BIOS will not enable deterministic performance control.
CPU Power Management set to Maximum Performance:
Allows selection of CPU power management methodology. Maximum Performance is typically selected for performance-centric workloads where it is acceptable to consume additional power to achieve the highest possible performance for the computing environment. This mode drives processor frequency to the maximum across all cores (although idled cores can still be frequency reduced by C-state enforcement through BIOS or OS mechanisms if enabled). This mode also offers the lowest latency of the CPU Power Management Mode options, so is always preferred for latency-sensitive environments. OS DBPM is another performance-per-watt option that relies on the operating system to dynamically control individual cores in order to save power.
Memory Frequency set to Maximum Performance:
Governs the BIOS memory frequency. The variables that govern maximum memory frequency include the maximum rated frequency of the DIMMs, the DIMMs per channel population, the processor choice, and this BIOS option. Additional power savings can be achieved by reducing the memory frequency, at the expense of reduced performance. Read-only unless System Profile is set to Custom.
Efficiency Optimized Mode Disabled:
This field enables/disabled Efficiency Optimized Mode. Efficiency Optimized Mode maximizes Performance-per-Watt by opportunistically reducing frequency/power.
NUMA Nodes Per Socket:
NUMA nodes per socket (NPS) field allows you to configure the memory NUMA domains per socket. The configuration can consist of one whole domain (NPS1), two domains (NPS2), or four domains (NPS4). In the case of a two-socket platform, an additional NPS profile is available to have whole system memory to be mapped as single NUMA domain (NPS0).
CCX as NUMA Domain:
In addition to selecting the number of NUMA domains via NPS option, the processor allows for making memory per CCX as NUMA domain. In the processor each CCD has a maximum of two CCXs with each CCX having a shared last-level cache (LLC, or L3 cache) for all cores. The CCX as NUMA domain option allows for each LLC to be configured as a NUMA domain so that for certain workloads pinning execution to a single NUMA domain can be done.
Adaptive Double DRAM Device Correction (ADDDC):
When Adaptive Double DRAM Device Correction (ADDDC) is enabled, failing DRAM’s are dynamically mapped out. When set to enabled, it can have some impact to system performance under certain workloads. This feature is applicable for x4 DIMMs only.
DCU Streamer Prefetcher:
Enables or disables Data Cache Unit (DCU) Streamer Prefetcher. This setting can affect performance, depending on the application running on the server. DCU streamer prefetchers detect multiple reads to a single cache line in a certain period of time and choose to load the following cache line to the L1 data caches. Recommended for High Performance Computing applications.
DCU IP Prefetcher:
Enables or disables Data Cache Unit (DCU) IP Prefetcher. DCU IP Prefetcher looks for sequential load history to determine whether to prefetch the data to the L1 caches.
Memory Frequency:
Governs the BIOS memory frequency. The variables that govern maximum memory frequency include the maximum rated frequency of the DIMMs, the DIMMs per channel population, the processor choice, and this BIOS option. Additional power savings can be achieved by reducing the memory frequency, at the expense of reduced performance.
Turbo Boost:
Governs the Boost Technology. This feature allows the processor cores to be automatically clocked up in frequency beyond the advertised processor speed. The amount of increased frequency (or 'turbo upside') one can expect from an EPYC processor depends on the fewer cores being exercised with work the higher the potential turbo upside. The potential drawback for Boost are mainly centered on increased power consumption and possible frequency jitter that can affect a small minority of latency-sensitive environments.
C1E:
When set to Enabled, the processor is allowed to switch to minimum performance state when idle.
CPU Interconnect Bus Link Power Management:
When Enabled, CPU interconnect bus link power management can reduce overall system power a bit while slightly reducing system performance.
CPU Performance:
Maximum Performance is typically selected for performance-centric workloads where it is acceptable to consume additional power to achieve the highest possible performance for the computing environment. This mode drives processor frequency to the maximum across all cores (although idled cores can still be frequency reduced by C-state enforcement through BIOS or OS mechanisms if enabled). This mode also offers the lowest latency of the CPU Power Management Mode options, so is always preferred.
Energy Efficient Policy:
The CPU uses the setting to manipulate the internal behavior of the processor and determines
whether to target higher performance or better power savings. The possible settings are: Performance, Balanced Performance, Balanced Energy, Energy Efficient.
Energy Efficient Turbo:
Permits Energy Efficient Turbo to be Enabled or Disabled.
Energy Efficient Turbo (EET) is a mode of operation where a processor's core frequency is adjusted within the turbo range based on workload.
Logical Processor:
Each processor core supports up to two logical processors. When set to Enabled, the BIOS reports all logical processors. When set to Disabled, the BIOS only reports one logical processor per core. Generally, higher processor count results in increased performance for most multi-threaded workloads and the recommendation is to keep this enabled. However, there are some floating point/scientific workloads, including HPC workloads, where disabling this feature may result in higher performance.
Memory Patrol Scrub:
Patrol Scrubbing searches the memory for errors and repairs correctable errors to prevent the accumulation of memory errors. When set to Disabled, no patrol scrubbing will occur. When set to Standard Mode, the entire memory array will be scrubbed once in a 24 hour period. When set to Extended Mode, the entire memory array will be scrubbed more frequently to further increase system reliability.
Memory Refresh Rate:
The memory controller will periodically refresh the data in memory. The frequency at which memory is normally refreshed is referred to as 1X refresh rate. When memory modules are operating at a higher than normal temperature or to further increase system reliability, the refresh rate can be set to 2X, but may have a negative impact on memory subsystem performance under some circumstances.
PCI ASPM L1 Link Power Management:
When Enabled, PCIe Advanced State Power Management (ASPM) can reduce overall system power
a bit while slightly reducing system performance.
NOTE: Some devices may not perform properly (they may hang or cause the system to hang)
when ASPM is enabled, for this reason L1 will only be enabled for validated qualified cards.
System Profile:
When set to Custom, you can change setting of each option. Under Custom mode when C States is enabled, Monitor/Mwait should also be Enabled.
Monitor/Mwait:
Specifies whether Monitor/Mwait instructions are enabled. Monitor/Mwait is only active when C States is set to Disabled.
Sub NUMA Cluster:
When Enabled, Sub NUMA Clustering (SNC) is a feature for breaking up the LLC into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. It improves average latency to the LLC.
Uncore Frequency:
Selects the Processor Uncore Frequency.
Dynamic mode allows processor to optimize power resources across the cores and uncore during runtime.
The optimization of the uncore frequency to either save power or optimize performance is influenced
by the setting of the Energy Efficient Policy.
Virtualization Technology:
When set to Enabled, the BIOS will enable processor Virtualization features and provide the virtualization support to the Operating System (OS) through the DMAR table. In general, only virtualized environments such as VMware(r) ESX (tm), Microsoft Hyper-V(r) , Red Hat(r) KVM, and other virtualized operating systems will take advantage of these features. Disabling this feature is not known to significantly alter the performance or power characteristics of the system, so leaving this option Enabled is advised for most cases.
nohz_full:
This kernel option sets adaptive tick mode (NOHZ_FULL) to specified processors. Since the number of interrupts is reduced to ones per second, latency-sensitive applications can take advantage of it.
Memory Interleaving:
When Enabled, memory interleaving is supported if a symmetric memory configuration is installed. When set to Disabled, the system supports Non-Uniform Memory Access (NUMA) (asymmetric) memory configurations. Channel interleaving is available with all configurations and is the intra-die memory interleave option. With channel interleaving the memory behind each UMC will be interleaved and seen as 1 NUMA domain per die.
Flag description origin markings:
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Indicates that the flag description came from the user flags file. |
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Indicates that the flag description came from the suite-wide flags file. |
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Indicates that the flag description came from a per-benchmark flags file. |
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2020 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.1.0.
Report generated on 2020-09-29 15:21:49 by SPEC CPU2017 flags formatter v5178.