SPEC(R) CPU2017 Floating Point Rate Result Huawei Huawei XH321 V5 (Intel Xeon Silver 4208) CPU2017 License: 3175 Test date: Oct-2018 Test sponsor: Huawei Hardware availability: Apr-2019 Tested by: Huawei Software availability: Dec-2018 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate --------------- ------- --------- --------- ------- --------- --------- 503.bwaves_r 32 1505 213 S 503.bwaves_r 32 1506 213 * 503.bwaves_r 32 1507 213 S 507.cactuBSSN_r 32 599 67.7 S 507.cactuBSSN_r 32 598 67.8 S 507.cactuBSSN_r 32 598 67.7 * 508.namd_r 32 523 58.1 S 508.namd_r 32 516 58.9 S 508.namd_r 32 518 58.7 * 510.parest_r 32 1782 47.0 S 510.parest_r 32 1778 47.1 S 510.parest_r 32 1781 47.0 * 511.povray_r 32 818 91.3 S 511.povray_r 32 806 92.7 S 511.povray_r 32 809 92.3 * 519.lbm_r 32 717 47.0 * 519.lbm_r 32 712 47.4 S 519.lbm_r 32 718 47.0 S 521.wrf_r 32 815 87.9 * 521.wrf_r 32 821 87.3 S 521.wrf_r 32 787 91.1 S 526.blender_r 32 572 85.2 S 526.blender_r 32 573 85.0 * 526.blender_r 32 574 85.0 S 527.cam4_r 32 713 78.5 S 527.cam4_r 32 708 79.1 * 527.cam4_r 32 706 79.3 S 538.imagick_r 32 473 168 S 538.imagick_r 32 487 163 S 538.imagick_r 32 474 168 * 544.nab_r 32 421 128 * 544.nab_r 32 430 125 S 544.nab_r 32 421 128 S 549.fotonik3d_r 32 1908 65.3 S 549.fotonik3d_r 32 1888 66.0 S 549.fotonik3d_r 32 1889 66.0 * 554.roms_r 32 1322 38.5 S 554.roms_r 32 1308 38.9 S 554.roms_r 32 1317 38.6 * ================================================================================= 503.bwaves_r 32 1506 213 * 507.cactuBSSN_r 32 598 67.7 * 508.namd_r 32 518 58.7 * 510.parest_r 32 1781 47.0 * 511.povray_r 32 809 92.3 * 519.lbm_r 32 717 47.0 * 521.wrf_r 32 815 87.9 * 526.blender_r 32 573 85.0 * 527.cam4_r 32 708 79.1 * 538.imagick_r 32 474 168 * 544.nab_r 32 421 128 * 549.fotonik3d_r 32 1889 66.0 * 554.roms_r 32 1317 38.6 * SPECrate2017_fp_base 80.1 SPECrate2017_fp_peak Not Run HARDWARE -------- CPU Name: Intel Xeon Silver 4208 Max MHz.: 3200 Nominal: 2100 Enabled: 16 cores, 2 chips, 2 threads/core Orderable: 1,2 chips Cache L1: 32 KB I + 32 KB D on chip per core L2: 1 MB I+D on chip per core L3: 11 MB I+D on chip per chip Other: None Memory: 384 GB (12 x 32 GB 2Rx4 PC4-2933Y-R, running at 2400) Storage: 1 x 1800 GB SAS, 10000 RPM Other: None SOFTWARE -------- OS: SUSE Linux Enterprise Server 12 SP4 (x86_64) 4.12.14-94.41-default Compiler: C/C++: Version 19.0.1.144 of Intel C/C++ Compiler Build 20181018 for Linux; Fortran: Version 19.0.1.144 of Intel Fortran Compiler Build 20181018 for Linux Parallel: No Firmware: Version 6.52 Released Mar-2019 File System: xfs System State: Run level 3 (multi-user) Base Pointers: 64-bit Peak Pointers: Not Applicable Other: None Submit Notes ------------ The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" General Notes ------------- Environment variables set by runcpu before the start of the run: LD_LIBRARY_PATH = "/spec2017/lib/ia32:/spec2017/lib/intel64" Binaries compiled on a system with 1x Intel Core i9-7900X CPU + 32GB RAM memory using Redhat Enterprise Linux 7.5 Transparent Huge Pages enabled by default Prior to runcpu invocation Filesystem page cache synced and cleared with: sync; echo 3> /proc/sys/vm/drop_caches runcpu command invoked through numactl i.e.: numactl --interleave=all runcpu Yes: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2) is mitigated in the system as tested and documented. Platform Notes -------------- BIOS configuration: Power Policy Set to Performance SNC Set to Enabled IMC Interleaving Set to 1-way Interleave XPT Prefetch Set to Enabled Sysinfo program /spec2017/bin/sysinfo Rev: r5974 of 2018-05-19 9bcde8f2999c33d61f64985e45859ea9 running on spec2 Mon Oct 1 19:49:05 2018 SUT (System Under Test) info as seen by some common utilities. For more information on this section, see https://www.spec.org/cpu2017/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Silver 4208 CPU @ 2.10GHz 2 "physical id"s (chips) 32 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 8 siblings : 16 physical 0: cores 0 1 2 3 4 5 6 7 physical 1: cores 0 1 2 3 4 5 6 7 From lscpu: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 32 On-line CPU(s) list: 0-31 Thread(s) per core: 2 Core(s) per socket: 8 Socket(s): 2 NUMA node(s): 2 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Silver 4208 CPU @ 2.10GHz Stepping: 6 CPU MHz: 2100.000 CPU max MHz: 3200.0000 CPU min MHz: 800.0000 BogoMIPS: 4200.00 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 11264K NUMA node0 CPU(s): 0-7,16-23 NUMA node1 CPU(s): 8-15,24-31 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single ssbd mba ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts pku ospke avx512_vnni flush_l1d arch_capabilities /proc/cpuinfo cache data cache size : 11264 KB From numactl --hardware WARNING: a numactl 'node' might or might not correspond to a physical chip. available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 node 0 size: 192848 MB node 0 free: 191897 MB node 1 cpus: 8 9 10 11 12 13 14 15 24 25 26 27 28 29 30 31 node 1 size: 193279 MB node 1 free: 192165 MB node distances: node 0 1 0: 10 21 1: 21 10 From /proc/meminfo MemTotal: 395395008 kB HugePages_Total: 0 Hugepagesize: 2048 kB From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 4 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12-SP4" VERSION_ID="12.4" PRETTY_NAME="SUSE Linux Enterprise Server 12 SP4" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12:sp4" uname -a: Linux spec2 4.12.14-94.41-default #1 SMP Wed Oct 31 12:25:04 UTC 2018 (3090901) x86_64 x86_64 x86_64 GNU/Linux Kernel self-reported vulnerability status: CVE-2017-5754 (Meltdown): Not affected CVE-2017-5753 (Spectre variant 1): Mitigation: __user pointer sanitization CVE-2017-5715 (Spectre variant 2): Mitigation: Indirect Branch Restricted Speculation, IBPB, IBRS_FW run-level 3 Oct 1 14:33 SPEC is set to: /spec2017 Filesystem Type Size Used Avail Use% Mounted on /dev/sda2 xfs 1.7T 11G 1.7T 1% / Additional information from dmidecode follows. WARNING: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS INSYDE Corp. 6.52 03/16/2019 Memory: 4x NO DIMM NO DIMM 12x Samsung M393A4K40CB2-CVF 32 GB 2 rank 2933, configured at 2400 (End of data from sysinfo program) Compiler Version Notes ---------------------- ============================================================================== CC 519.lbm_r(base) 538.imagick_r(base) 544.nab_r(base) ------------------------------------------------------------------------------ Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.1.144 Build 20181018 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== CXXC 508.namd_r(base) 510.parest_r(base) ------------------------------------------------------------------------------ Intel(R) C++ Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.1.144 Build 20181018 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== CC 511.povray_r(base) 526.blender_r(base) ------------------------------------------------------------------------------ Intel(R) C++ Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.1.144 Build 20181018 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.1.144 Build 20181018 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== FC 507.cactuBSSN_r(base) ------------------------------------------------------------------------------ Intel(R) C++ Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.1.144 Build 20181018 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.1.144 Build 20181018 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.1.144 Build 20181018 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== FC 503.bwaves_r(base) 549.fotonik3d_r(base) 554.roms_r(base) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.1.144 Build 20181018 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== CC 521.wrf_r(base) 527.cam4_r(base) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.1.144 Build 20181018 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.1.144 Build 20181018 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ Base Compiler Invocation ------------------------ C benchmarks: icc -m64 -std=c11 C++ benchmarks: icpc -m64 Fortran benchmarks: ifort -m64 Benchmarks using both Fortran and C: ifort -m64 icc -m64 -std=c11 Benchmarks using both C and C++: icpc -m64 icc -m64 -std=c11 Benchmarks using Fortran, C, and C++: icpc -m64 icc -m64 -std=c11 ifort -m64 Base Portability Flags ---------------------- 503.bwaves_r: -DSPEC_LP64 507.cactuBSSN_r: -DSPEC_LP64 508.namd_r: -DSPEC_LP64 510.parest_r: -DSPEC_LP64 511.povray_r: -DSPEC_LP64 519.lbm_r: -DSPEC_LP64 521.wrf_r: -DSPEC_LP64 -DSPEC_CASE_FLAG -convert big_endian 526.blender_r: -DSPEC_LP64 -DSPEC_LINUX -funsigned-char 527.cam4_r: -DSPEC_LP64 -DSPEC_CASE_FLAG 538.imagick_r: -DSPEC_LP64 544.nab_r: -DSPEC_LP64 549.fotonik3d_r: -DSPEC_LP64 554.roms_r: -DSPEC_LP64 Base Optimization Flags ----------------------- C benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 C++ benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 Fortran benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -auto -nostandard-realloc-lhs -align array32byte Benchmarks using both Fortran and C: -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -auto -nostandard-realloc-lhs -align array32byte Benchmarks using both C and C++: -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 Benchmarks using Fortran, C, and C++: -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -auto -nostandard-realloc-lhs -align array32byte The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.2019-04-02.html http://www.spec.org/cpu2017/flags/Huawei-Platform-Settings-SKL-V1.9-revC.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.2019-04-02.xml http://www.spec.org/cpu2017/flags/Huawei-Platform-Settings-SKL-V1.9-revC.xml SPEC is a registered trademark of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact info@spec.org. Copyright 2017-2019 Standard Performance Evaluation Corporation Tested with SPEC CPU2017 v1.0.5 on 2018-10-01 19:49:04-0400. Report generated on 2019-05-15 13:35:20 by CPU2017 ASCII formatter v6067. Originally published on 2019-05-14.