SPEC CPU(R)2017 Floating Point Rate Result Cisco Systems Cisco UCS C480 M5 (Intel Xeon Gold 5120, 2.20 GHz) CPU2017 License: 9019 Test date: Feb-2019 Test sponsor: Cisco Systems Hardware availability: Aug-2017 Tested by: Cisco Systems Software availability: Oct-2018 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate --------------- ------- --------- --------- ------- --------- --------- 503.bwaves_r 112 1411 796 S 112 1410 796 * 503.bwaves_r 112 1410 796 S 112 1410 797 S 503.bwaves_r 112 1411 796 * 112 1413 795 S 507.cactuBSSN_r 112 608 233 * 112 608 233 S 507.cactuBSSN_r 112 608 233 S 112 608 233 * 507.cactuBSSN_r 112 609 233 S 112 609 233 S 508.namd_r 112 487 219 * 112 485 220 * 508.namd_r 112 486 219 S 112 485 219 S 508.namd_r 112 488 218 S 112 483 220 S 510.parest_r 112 1703 172 * 112 1703 172 * 510.parest_r 112 1703 172 S 112 1701 172 S 510.parest_r 112 1701 172 S 112 1706 172 S 511.povray_r 112 795 329 * 112 690 379 S 511.povray_r 112 794 329 S 112 701 373 S 511.povray_r 112 798 328 S 112 694 377 * 519.lbm_r 112 638 185 S 112 637 185 * 519.lbm_r 112 638 185 * 112 637 185 S 519.lbm_r 112 637 185 S 112 638 185 S 521.wrf_r 112 713 352 S 112 702 357 * 521.wrf_r 112 716 351 S 112 700 358 S 521.wrf_r 112 714 351 * 112 702 357 S 526.blender_r 112 612 279 S 112 611 279 * 526.blender_r 112 611 279 S 112 610 280 S 526.blender_r 112 612 279 * 112 612 279 S 527.cam4_r 112 607 323 * 112 594 330 * 527.cam4_r 112 607 323 S 112 596 329 S 527.cam4_r 112 609 322 S 112 594 330 S 538.imagick_r 112 448 621 * 112 449 621 * 538.imagick_r 112 448 622 S 112 450 619 S 538.imagick_r 112 449 621 S 112 448 621 S 544.nab_r 112 404 466 S 112 404 466 S 544.nab_r 112 405 466 * 112 402 469 S 544.nab_r 112 405 466 S 112 403 468 * 549.fotonik3d_r 112 1734 252 S 112 1734 252 S 549.fotonik3d_r 112 1736 251 S 112 1734 252 * 549.fotonik3d_r 112 1735 252 * 112 1736 251 S 554.roms_r 112 1205 148 * 112 1207 147 S 554.roms_r 112 1200 148 S 112 1202 148 S 554.roms_r 112 1212 147 S 112 1203 148 * ================================================================================= 503.bwaves_r 112 1411 796 * 112 1410 796 * 507.cactuBSSN_r 112 608 233 * 112 608 233 * 508.namd_r 112 487 219 * 112 485 220 * 510.parest_r 112 1703 172 * 112 1703 172 * 511.povray_r 112 795 329 * 112 694 377 * 519.lbm_r 112 638 185 * 112 637 185 * 521.wrf_r 112 714 351 * 112 702 357 * 526.blender_r 112 612 279 * 112 611 279 * 527.cam4_r 112 607 323 * 112 594 330 * 538.imagick_r 112 448 621 * 112 449 621 * 544.nab_r 112 405 466 * 112 403 468 * 549.fotonik3d_r 112 1735 252 * 112 1734 252 * 554.roms_r 112 1205 148 * 112 1203 148 * SPECrate(R)2017_fp_base 298 SPECrate(R)2017_fp_peak 302 HARDWARE -------- CPU Name: Intel Xeon Gold 5120 Max MHz: 3200 Nominal: 2200 Enabled: 56 cores, 4 chips, 2 threads/core Orderable: 2,4 Chips Cache L1: 32 KB I + 32 KB D on chip per core L2: 1 MB I+D on chip per core L3: 19.25 MB I+D on chip per chip Other: None Memory: 1536 GB (48 x 32 GB 2Rx4 PC4-2666V-R, running at 2400) Storage: 1 x 1 TB HDD, 7.2K RPM Other: None SOFTWARE -------- OS: SUSE Linux Enterprise Server 12 SP2 (x86_64) 4.4.120-92.70-default Compiler: C/C++: Version 19.0.0.117 of Intel C/C++ Compiler for Linux; Fortran: Version 19.0.0.117 of Intel Fortran Compiler for Linux Parallel: No Firmware: Version 3.1.3e released Jun-2018 File System: xfs System State: Run level 3 (multi-user) Base Pointers: 64-bit Peak Pointers: 64-bit Other: None Power Management: -- Submit Notes ------------ The taskset mechanism was used to bind copies to processors. The config file option 'submit' was used to generate taskset commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" General Notes ------------- Environment variables set by runcpu before the start of the run: LD_LIBRARY_PATH = "/home/cpu2017/lib/ia32:/home/cpu2017/lib/intel64" Binaries compiled on a system with 1x Intel Core i9-7900X CPU + 32GB RAM memory using Redhat Enterprise Linux 7.5 Transparent Huge Pages enabled by default Prior to runcpu invocation Filesystem page cache synced and cleared with: sync; echo 3> /proc/sys/vm/drop_caches Yes: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2) is mitigated in the system as tested and documented. Platform Notes -------------- BIOS Settings: Intel HyperThreading Technology set to Enabled CPU performance set to Enterprise Power Performance Tuning set to OS Controls SNC set to Enabled IMC Interleaving set to 1-way Interleave Patrol Scrub set to Disabled Sysinfo program /home/cpu2017/bin/sysinfo Rev: r5974 of 2018-05-19 9bcde8f2999c33d61f64985e45859ea9 running on linux-9r4j Sun Feb 3 05:58:13 2019 SUT (System Under Test) info as seen by some common utilities. For more information on this section, see https://www.spec.org/cpu2017/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Gold 5120 CPU @ 2.20GHz 4 "physical id"s (chips) 112 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 14 siblings : 28 physical 0: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 physical 1: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 physical 2: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 physical 3: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 From lscpu: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 112 On-line CPU(s) list: 0-111 Thread(s) per core: 2 Core(s) per socket: 14 Socket(s): 4 NUMA node(s): 8 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Gold 5120 CPU @ 2.20GHz Stepping: 4 CPU MHz: 2599.999 CPU max MHz: 3200.0000 CPU min MHz: 1000.0000 BogoMIPS: 4395.29 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 19712K NUMA node0 CPU(s): 0-3,7-9,56-59,63-65 NUMA node1 CPU(s): 4-6,10-13,60-62,66-69 NUMA node2 CPU(s): 14-17,21-23,70-73,77-79 NUMA node3 CPU(s): 18-20,24-27,74-76,80-83 NUMA node4 CPU(s): 28-31,35-37,84-87,91-93 NUMA node5 CPU(s): 32-34,38-41,88-90,94-97 NUMA node6 CPU(s): 42-45,49-51,98-101,105-107 NUMA node7 CPU(s): 46-48,52-55,102-104,108-111 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch ida arat epb invpcid_single pln pts dtherm hwp hwp_act_window hwp_epp hwp_pkg_req intel_pt rsb_ctxsw spec_ctrl stibp retpoline kaiser tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx avx512f avx512dq rdseed adx smap clflushopt clwb avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 cqm_llc cqm_occup_llc /proc/cpuinfo cache data cache size : 19712 KB From numactl --hardware WARNING: a numactl 'node' might or might not correspond to a physical chip. available: 8 nodes (0-7) node 0 cpus: 0 1 2 3 7 8 9 56 57 58 59 63 64 65 node 0 size: 192093 MB node 0 free: 183106 MB node 1 cpus: 4 5 6 10 11 12 13 60 61 62 66 67 68 69 node 1 size: 193528 MB node 1 free: 187660 MB node 2 cpus: 14 15 16 17 21 22 23 70 71 72 73 77 78 79 node 2 size: 193528 MB node 2 free: 187649 MB node 3 cpus: 18 19 20 24 25 26 27 74 75 76 80 81 82 83 node 3 size: 193528 MB node 3 free: 187936 MB node 4 cpus: 28 29 30 31 35 36 37 84 85 86 87 91 92 93 node 4 size: 193528 MB node 4 free: 187488 MB node 5 cpus: 32 33 34 38 39 40 41 88 89 90 94 95 96 97 node 5 size: 193528 MB node 5 free: 187785 MB node 6 cpus: 42 43 44 45 49 50 51 98 99 100 101 105 106 107 node 6 size: 193528 MB node 6 free: 187911 MB node 7 cpus: 46 47 48 52 53 54 55 102 103 104 108 109 110 111 node 7 size: 193525 MB node 7 free: 187845 MB node distances: node 0 1 2 3 4 5 6 7 0: 10 11 21 21 21 21 31 31 1: 11 10 21 21 21 21 31 31 2: 21 21 10 11 31 31 21 21 3: 21 21 11 10 31 31 21 21 4: 21 21 31 31 10 11 21 21 5: 21 21 31 31 11 10 21 21 6: 31 31 21 21 21 21 10 11 7: 31 31 21 21 21 21 11 10 From /proc/meminfo MemTotal: 1583913248 kB HugePages_Total: 0 Hugepagesize: 2048 kB From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 2 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12-SP2" VERSION_ID="12.2" PRETTY_NAME="SUSE Linux Enterprise Server 12 SP2" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12:sp2" uname -a: Linux linux-9r4j 4.4.120-92.70-default #1 SMP Wed Mar 14 15:59:43 UTC 2018 (52a83de) x86_64 x86_64 x86_64 GNU/Linux Kernel self-reported vulnerability status: CVE-2017-5754 (Meltdown): Mitigation: PTI CVE-2017-5753 (Spectre variant 1): Mitigation: __user pointer sanitization CVE-2017-5715 (Spectre variant 2): Mitigation: IBRS+IBPB run-level 3 Dec 25 08:59 SPEC is set to: /home/cpu2017 Filesystem Type Size Used Avail Use% Mounted on /dev/sda1 xfs 930G 80G 851G 9% / Additional information from dmidecode follows. WARNING: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Cisco Systems, Inc. C480M5.3.1.3e.0.0613181101 06/13/2018 Memory: 48x 0xCE00 M393A4K40BB2-CTD 32 GB 2 rank 2666, configured at 2400 (End of data from sysinfo program) Compiler Version Notes ---------------------- ============================================================================== C | 519.lbm_r(base, peak) 538.imagick_r(base, peak) | 544.nab_r(base, peak) ------------------------------------------------------------------------------ Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.0.117 Build 20180804 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C++ | 508.namd_r(base, peak) 510.parest_r(base, peak) ------------------------------------------------------------------------------ Intel(R) C++ Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.0.117 Build 20180804 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C++, C | 511.povray_r(base, peak) 526.blender_r(base, peak) ------------------------------------------------------------------------------ Intel(R) C++ Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.0.117 Build 20180804 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.0.117 Build 20180804 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C++, C, Fortran | 507.cactuBSSN_r(base, peak) ------------------------------------------------------------------------------ Intel(R) C++ Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.0.117 Build 20180804 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.0.117 Build 20180804 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.0.117 Build 20180804 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran | 503.bwaves_r(base, peak) 549.fotonik3d_r(base, peak) | 554.roms_r(base, peak) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.0.117 Build 20180804 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran, C | 521.wrf_r(base, peak) 527.cam4_r(base, peak) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.0.117 Build 20180804 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 19.0.0.117 Build 20180804 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ Base Compiler Invocation ------------------------ C benchmarks: icc -m64 -std=c11 C++ benchmarks: icpc -m64 Fortran benchmarks: ifort -m64 Benchmarks using both Fortran and C: ifort -m64 icc -m64 -std=c11 Benchmarks using both C and C++: icpc -m64 icc -m64 -std=c11 Benchmarks using Fortran, C, and C++: icpc -m64 icc -m64 -std=c11 ifort -m64 Base Portability Flags ---------------------- 503.bwaves_r: -DSPEC_LP64 507.cactuBSSN_r: -DSPEC_LP64 508.namd_r: -DSPEC_LP64 510.parest_r: -DSPEC_LP64 511.povray_r: -DSPEC_LP64 519.lbm_r: -DSPEC_LP64 521.wrf_r: -DSPEC_LP64 -DSPEC_CASE_FLAG -convert big_endian 526.blender_r: -DSPEC_LP64 -DSPEC_LINUX -funsigned-char 527.cam4_r: -DSPEC_LP64 -DSPEC_CASE_FLAG 538.imagick_r: -DSPEC_LP64 544.nab_r: -DSPEC_LP64 549.fotonik3d_r: -DSPEC_LP64 554.roms_r: -DSPEC_LP64 Base Optimization Flags ----------------------- C benchmarks: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 C++ benchmarks: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 Fortran benchmarks: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -auto -nostandard-realloc-lhs -align array32byte Benchmarks using both Fortran and C: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -auto -nostandard-realloc-lhs -align array32byte Benchmarks using both C and C++: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 Benchmarks using Fortran, C, and C++: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -auto -nostandard-realloc-lhs -align array32byte Peak Compiler Invocation ------------------------ C benchmarks: icc -m64 -std=c11 C++ benchmarks: icpc -m64 Fortran benchmarks: ifort -m64 Benchmarks using both Fortran and C: ifort -m64 icc -m64 -std=c11 Benchmarks using both C and C++: icpc -m64 icc -m64 -std=c11 Benchmarks using Fortran, C, and C++: icpc -m64 icc -m64 -std=c11 ifort -m64 Peak Portability Flags ---------------------- Same as Base Portability Flags Peak Optimization Flags ----------------------- C benchmarks: 519.lbm_r: -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 538.imagick_r: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 544.nab_r: Same as 538.imagick_r C++ benchmarks: 508.namd_r: -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 510.parest_r: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 Fortran benchmarks: 503.bwaves_r: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -auto -nostandard-realloc-lhs -align array32byte 549.fotonik3d_r: Same as 503.bwaves_r 554.roms_r: -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -auto -nostandard-realloc-lhs -align array32byte Benchmarks using both Fortran and C: -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -auto -nostandard-realloc-lhs -align array32byte Benchmarks using both C and C++: 511.povray_r: -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 526.blender_r: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 Benchmarks using Fortran, C, and C++: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -auto -nostandard-realloc-lhs -align array32byte The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2017/flags/Intel-ic19.0-official-linux64.2019-01-15.html http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2017/flags/Intel-ic19.0-official-linux64.2019-01-15.xml http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.xml SPEC CPU and SPECrate are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ---------------------------------------------------------------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact info@spec.org. Copyright 2017-2020 Standard Performance Evaluation Corporation Tested with SPEC CPU(R)2017 v1.0.5 on 2019-02-03 05:58:12-0500. Report generated on 2020-07-01 13:41:58 by CPU2017 text formatter v6255. Originally published on 2019-02-19.