CPU2017 Flag Description
Supermicro SuperStorage 5049P-E1CR45H (X11SPL-F , Intel Xeon Silver 4112)

Copyright © 2016 Intel Corporation. All Rights Reserved.

Base Compiler Invocation

C benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using Fortran, C, and C++

Peak Compiler Invocation

C benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using Fortran, C, and C++

Base Portability Flags

603.bwaves_s

607.cactuBSSN_s

619.lbm_s

621.wrf_s

627.cam4_s

628.pop2_s

638.imagick_s

644.nab_s

649.fotonik3d_s

654.roms_s

Peak Portability Flags

603.bwaves_s

607.cactuBSSN_s

619.lbm_s

621.wrf_s

627.cam4_s

628.pop2_s

638.imagick_s

644.nab_s

649.fotonik3d_s

654.roms_s

Base Optimization Flags

C benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using Fortran, C, and C++

Peak Optimization Flags

C benchmarks

619.lbm_s

638.imagick_s

644.nab_s

Fortran benchmarks

603.bwaves_s

649.fotonik3d_s

654.roms_s

Benchmarks using both Fortran and C

621.wrf_s

627.cam4_s

628.pop2_s

Benchmarks using Fortran, C, and C++

607.cactuBSSN_s

Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.

Commands and Options Used to Submit Benchmark Runs

submit= MYMASK=`printf '0x%x' $((1<<$SPECCOPYNUM))`; /usr/bin/taskset $MYMASK $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command, using taskset, is used for Linux64 systems without numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:
submit= numactl --localalloc --physcpubind=$SPECCOPYNUM $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command is used for Linux64 systems with support for numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:

Shell, Environment, and Other Software Settings

numactl --interleave=all "runspec command"
Launching a process with numactl --interleave=all sets the memory interleave policy so that memory will be allocated using round robin on nodes. When memory cannot be allocated on the current interleave target fall back to other nodes.
KMP_STACKSIZE
Specify stack size to be allocated for each thread.
KMP_AFFINITY
Syntax: KMP_AFFINITY=[<modifier>,...]<type>[,<permute>][,<offset>]
The value for the environment variable KMP_AFFINITY affects how the threads from an auto-parallelized program are scheduled across processors.
It applies to binaries built with -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows).
modifier:
    granularity=fine Causes each OpenMP thread to be bound to a single thread context.
type:
    compact Specifying compact assigns the OpenMP thread <n>+1 to a free thread context as close as possible to the thread context where the <n> OpenMP thread was placed.
    scatter Specifying scatter distributes the threads as evenly as possible across the entire system.
permute: The permute specifier is an integer value controls which levels are most significant when sorting the machine topology map. A value for permute forces the mappings to make the specified number of most significant levels of the sort the least significant, and it inverts the order of significance.
offset: The offset specifier indicates the starting position for thread assignment.

Please see the Thread Affinity Interface article in the Intel Composer XE Documentation for more details.

Example: KMP_AFFINITY=granularity=fine,scatter
Specifying granularity=fine selects the finest granularity level and causes each OpenMP or auto-par thread to be bound to a single thread context.
This ensures that there is only one thread per core on cores supporting HyperThreading Technology
Specifying scatter distributes the threads as evenly as possible across the entire system.
Hence a combination of these two options, will spread the threads evenly across sockets, with one thread per physical core.

Example: KMP_AFFINITY=compact,1,0
Specifying compact will assign the n+1 thread to a free thread context as close as possible to thread n.
A default granularity=core is implied if no granularity is explicitly specified.
Specifying 1,0 sets permute and offset values of the thread assignment.
With a permute value of 1, thread n+1 is assigned to a consecutive core. With an offset of 0, the process's first thread 0 will be assigned to thread 0.
The same behavior is exhibited in a multisocket system.
OMP_NUM_THREADS
Sets the maximum number of threads to use for OpenMP* parallel regions if no other value is specified in the application. This environment variable applies to both -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores: export OMP_NUM_THREADS=8
Set stack size to unlimited
The command "ulimit -s unlimited" is used to set the stack size limit to unlimited.
Free the file system page cache
The command "echo 1> /proc/sys/vm/drop_caches" is used to free up the filesystem page cache.

Red Hat Specific features

Transparent Huge Pages
On RedHat EL 6 and later, Transparent Hugepages increase the memory page size from 4 kilobytes to 2 megabytes. Transparent Hugepages provide significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead.
Hugepages are used by default unless the /sys/kernel/mm/redhat_transparent_hugepage/enabled field is changed from its RedHat EL6 default of 'always'.

Firmware / BIOS / Microcode Settings

ENERGY_PERF_BIAS_CFG mode:
This BIOS option allows for processor performance and power optmization. Available settings are:
Power Techonology:
Switch processor power management features. If value "Custom" is set, Customer can define the values of all power management setup items.
Power Performance Tuning:
Allows the OS or BIOS to control the Energy Performance Bias.
Patrol Scrub:
Enable or disable the ability to proactively search the system memory, repairing correctable errors.
CPU C6 Report:
Allows the BIOS to report the CPU C6 State (ACPI C3) to the operating system. During the CPU C6 State, the power to all cache is turned off.
Hyper-Threading (ALL):
Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology). When Disabled only one thread per enabled core is enabled.
Enforce POR:
Enable to enforce Plan Of Record restrictions for DDR4 frequency and voltage programming. Memory speeds will be capped at Intel guidelines. Disabling allows user selection of additional supported memory speeds.
Memory Frequency:
Selects desired memory frequecy (within populated memory limits).
Intel Virtualization Technology:
When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology
Hardware P-states:
This setting allows the user to select between OS and hardware-controlled P-states. Selecting Native Mode allows the OS to choose a P-state. Selecting Out of Band Mode allows the hardware to autonomously choose a P-state without OS guidance. Selecting Native Mode with No Legacy Support functions as Native Mode with no support for older hardware.
SNC (Sub NUMA Cluster):
Sub-NUMA Clusters (SNC) is a feature that provides similar localization benefits as Cluster-On-Die (COD), without some of COD's downsides. SNC breaks up the LLC into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. SNC improves average latency to the LLC.
IMC Interleaving:
This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs). If 2 iMCs are 2-way interleaved, the channel population behind both iMCs must be identical. For iMCs in 1-way interleave, there are no requirements for matching across iMCs.
LLC dead line alloc:
In the Skylake-SP non-inclusive cache scheme, MLC evictions are filled into the LLC. When lines are evicted from the MLC, the core can flag them as "dead" (i.e., not likely to be read again). The LLC has the option to drop dead lines and not fill them in the LLC. If the Dead Line LLC Alloc feature is disabled, dead lines will always be dropped and will never fill into the LLC. This can help save space in the LLC and prevent the LLC from evicting useful data. However, if the Dead Line LLC Alloc feature is enabled, the LLC can opportunistically fill dead lines into the LLC if there is free space available.
Stale AtoS:
The in-memory directory has three states: I, A, and S. I (invalid) state means the data is clean and does not exist in any other socket's cache. The A (snoopAll) state means the data may exist in another socket in exclusive or modified state. S (Shared) state means the data is clean and may be shared across one or more socket's caches. When doing a read to memory, if the directory line is in the A state we must snoop all the other sockets because another socket may have the line in modified state. If this is the case, the snoop will return the modified data. However, it may be the case that a line is read in A state and all the snoops come back a miss. This can happen if another socket read the line earlier and then silently dropped it from its cache without modifying it. If Stale AtoS feature is enabled, in the situation where a line in A state returns only snoop misses, the line will transition to S state. That way, subsequent reads to the line will encounter it in S state and not have to snoop, saving latency and snoop bandwidth. Stale AtoS may be beneficial in a workload where there are many cross-socket reads.
LLC prefetch:
The LLC prefetcher is an additional prefetch mechanism on top of the existing prefetchers that prefetch data into the core Data Cache Unit (DCU) and Mid-Level Cache (MLC). Enabling LLC prefetch gives the core prefetcher the ability to prefetch data directly into the LLC without necessarily filling into the MLC.
XPT prefetch:
This feature allows an LLC read request to be speculatively duplicated and sent concurrently to the appropriate MC (Memory Controller). These speculative MC reads are sent when an LLC miss is likely based on recent LLC history. IIf an LLC miss does occur, the MC read is already in flight so the requested data will be returned more quickly.
SDDC Plus One:
Which is the enhanced feature to SDDC, will spare the faulty DRAM device out after an SDDC event has occurred. After the event, the SDDC+1 ECC mode is activated to protect against any additional memory failure caused by a ‘single-bit’ error in the same memory rank.
ADDDC Sparing:
Which is an improved feature of ADDDC, will allow the error correction code to correct an error caused by the failure of two DRAM devices or by a single-bit error that is beyond a device failure in the lockstep mode. ADDDC+1 will not issue a performance penalty before a device fails. Please note that virtual lockstep mode will only start to work for ADDDC after a faulty DRAM module is spared out at Bank granularity or Rank granularity.

Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.2017-12-21.html,
http://www.spec.org/cpu2017/flags/Supermicro-Platform-Settings-V1.2-SKL-revD.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.2017-12-21.xml,
http://www.spec.org/cpu2017/flags/Supermicro-Platform-Settings-V1.2-SKL-revD.xml.

For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2018 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.0.5.
Report generated on 2018-10-31 19:09:55 by SPEC CPU2017 flags formatter v5178.