Select "minimal" mode when installing the operating system,so that many services are not installed,this will reduce the consumption of resources by the operating system itself. And then only install necessary files of cpu test by yum.
Set this environment variable to "performance" to enable cores to run at performance mode. "scaling_governor" is a configuration file in Linux's "cpufreq" model. There are five mode in "scaling_governor" which are performance, powersave, userspace, ondemand, and conservative. Setting it to "performance" can lock the CPU's frequency at top speed without adjusting dynamically,which may require additional power. Setting it "powersave" means CPU will work at the minimum frequency; setting it to "userspace" provides the corresponding interface for the user-mode application program to adjust the frequency of CPU; "ondemand" means quick dynamic adjustment of CPU frequency on demand, and will reach the maximum frequency; "conservative" means frequency will be adjusted on demand. We use "cpupower frequency-set -g performance" to set this environment variable to "performance".
Set this environment variable to "yes" to enable applications to use large pages.
Setting this environment variable is necessary to enable applications to use large pages.
This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm In some cases, setting this option to Disabled may improve performance.Users should only disable this option after performing application benchmarking to verify improved performance in their environment. Hardware Prefetching is typically accomplished by having a dedicated hardware mechanism in the processor that watches the stream of instructions or data being requested by the executing program, recognizes the next few elements that the program might need based on this stream and prefetches into the processor's cache. The default setting is Enable.
Enabling this option allows the processor cores to automatically increase its frequency and increasing performance if it is running below power, temperature.
Enabling this option allows to use processor resources more efficiently, enabling multiple threads to run on each core and increases processor throughput, improving overall performance on threaded software.
This BIOS setting allows the memory to be clocked to the highest supported frequency.
If virtualization is not used, this option should be set to "Disabled", this can result in slight performance liftings and energy savings
This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs), Memory could be interleaved across sockets, memory controllers, DDR channels, Ranks. Memory is interleaved for performance and thermal distribution.
If IMC Interleaving is set to 2-way, addresses will be interleaved between the two IMCs.
If IMC Interleaving is set to 1-way, there will be no interleaving.
If IMC Interleaving is set to auto, it depends on the SNC (Sub NUMA Clustering) setting, when SNC is set to enbaled, the IMC Interleaving will be 1-way interleave, SNC is set to disabled, the IMC Interleaving will be 2-way interleave.
If SNC is disabled, IMC Interleaving should be set to 2-way. If SNC is enabled, IMC Interleaving should be set to 1-way.
SNC breaks up the last level cache (LLC) into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. SNC improves average latency to the LLC and memory. SNC is a replacement for the cluster on die (COD) feature found in previous processor families. For a multi-socketed system, all SNC clusters are mapped to unique NUMA (Non Uniform Memory Access) domains.
SNC AUTO supports 1-cluster or 2-clusters depending on IMC interleave. SNC and IMC interleave both AUTO will support 1-cluster 2-way IMC interleave.
SNC Enable supports Full SNC (2 clusters) and 1-way IMC interleave. Utilizes LLC capacity more efficiently and reduces latency due to core/IMC proximity. This may provide performance improvement on NUMA-aware operating systems.
SNC disable supports 1-cluster and 2-way IMC interleave, the LLC is treated as one cluster.
In some Intel CPU caching schemes, mid-level cache (MLC) evictions are filled into the last level cache (LLC). If a line is evicted from the MLC to the LLC, the core can flag the evicted MLC lines as "dead". This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if the option is disabled.
Values for this BIOS option can be:
Disabled: Disabling this option can save space in the LLC by never filling MLC dead lines into the LLC.
Enabled: Opportunistically fill MLC dead lines in LLC, if space is available.
This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit (DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.
Values for this BIOS option can be:
Disabled: Disables the LLC prefetcher. The other core prefetchers are unaffected.
Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.
The Xtended Prediction Table (XPT) prefetcher exists on top of other prefetchers that can prefetch data into the DCU, MLC, and LLC. The XPT prefetcher will issue a speculative DRAM read request in parallel to an LLC lookup. This prefetch bypasses the LLC, saving latency. In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.
Values for this BIOS option can be:
Enabled: Allows a read request sent to the LLC to speculatively issue a copy of the read to DRAM.
Disabled: Read requests to the LLC are not allowed to send a speculative read to DRAM.