SPEC(R) CINT2006 Summary Hewlett Packard Enterprise ProLiant DL385 Gen10 (2.10 GHz, AMD EPYC 7281) Test Sponsor: HPE Sat Nov 25 04:03:42 2017 CPU2006 License: 3 Test date: Nov-2017 Test sponsor: HPE Hardware availability: Nov-2017 Tested by: HPE Software availability: Sep-2017 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 64 650 963 S 400.perlbench 64 660 947 S 400.perlbench 64 652 959 * 401.bzip2 64 951 649 S 401.bzip2 64 946 653 S 401.bzip2 64 949 651 * 403.gcc 64 583 884 S 403.gcc 64 580 889 * 403.gcc 64 577 893 S 429.mcf 64 462 1260 * 429.mcf 64 463 1260 S 429.mcf 64 462 1260 S 445.gobmk 64 737 911 S 445.gobmk 64 738 910 * 445.gobmk 64 749 896 S 456.hmmer 64 307 1950 * 456.hmmer 64 310 1930 S 456.hmmer 64 305 1960 S 458.sjeng 64 919 842 * 458.sjeng 64 917 844 S 458.sjeng 64 920 842 S 462.libquantum 64 116 11500 S 462.libquantum 64 115 11500 S 462.libquantum 64 116 11500 * 464.h264ref 64 1116 1270 S 464.h264ref 64 1117 1270 S 464.h264ref 64 1117 1270 * 471.omnetpp 64 557 719 S 471.omnetpp 64 556 720 * 471.omnetpp 64 553 723 S 473.astar 64 618 727 S 473.astar 64 618 728 * 473.astar 64 617 728 S 483.xalancbmk 64 348 1270 * 483.xalancbmk 64 352 1260 S 483.xalancbmk 64 345 1280 S ============================================================================== 400.perlbench 64 652 959 * 401.bzip2 64 949 651 * 403.gcc 64 580 889 * 429.mcf 64 462 1260 * 445.gobmk 64 738 910 * 456.hmmer 64 307 1950 * 458.sjeng 64 919 842 * 462.libquantum 64 116 11500 * 464.h264ref 64 1117 1270 * 471.omnetpp 64 556 720 * 473.astar 64 618 728 * 483.xalancbmk 64 348 1270 * SPECint(R)_rate_base2006 1210 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: AMD EPYC 7281 CPU Characteristics: AMD Turbo CORE technology up to 2.70 GHz CPU MHz: 2100 FPU: Integrated CPU(s) enabled: 32 cores, 2 chips, 16 cores/chip, 2 threads/core CPU(s) orderable: 1, 2 chip(s) Primary Cache: 64 KB I + 32 KB D on chip per core Secondary Cache: 512 KB I+D on chip per core L3 Cache: 32 MB I+D on chip per chip, 4 MB shared / 2 cores Other Cache: None Memory: 1 TB (16 x 64 GB 4Rx4 PC4-2666V-L) Disk Subsystem: 1 x 400 GB SAS SSD, RAID 0 Other Hardware: None SOFTWARE -------- Operating System: SUSE Linux Enterprise Server 12 (x86_64) SP3 Kernel 4.4.73-5-default Compiler: C/C++: Version 4.5.2.1 of x86 Open64 Compiler Suite (from AMD) Auto Parallel: No File System: xfs System State: Run level 3 (multi-user) Base Pointers: 32/64-bit Peak Pointers: Not Applicable Other Software: MicroQuill SmartHeap 10.0 32-bit Library for Linux Submit Notes ------------ The config file option 'submit' was used. 'numactl' was used to bind copies to the cores. See the configuration file for details. Operating System Notes ---------------------- 'ulimit -s unlimited' was used to set environment stack size 'ulimit -l 2097152' was used to set environment locked pages in memory limit runspec command invoked through numactl i.e.: numactl --interleave=all runspec Set dirty_ratio=8 to limit dirty cache to 8% of memory Set swappiness=1 to swap only if necessary Set zone_reclaim_mode=1 to free local node memory and avoid remote memory sync then drop_caches=3 to reset caches before invoking runcpu Linux governor set to performance with cpupower "cpupower frequency-set -r -g performance" Transparent huge pages were enabled for this run (OS default) Set vm/nr_hugepages=57344 in /etc/sysctl.conf mount -t hugetlbfs nodev /mnt/hugepages Platform Notes -------------- BIOS Configuration: Thermal Configuration set to Maximum Cooling Performance Determinism set to Power Deterministic Memory Patrol Scrubbing set to Disabled Workload Pofile set to General Throughput Compute Minimum Processor Idle Power Core C-State set to C6 State General Notes ------------- Environment variables set by runspec before the start of the run: HUGETLB_LIMIT = "896" LD_LIBRARY_PATH = "/home/cpu2006/amd1603-rate-libs-revB/32:/home/cpu2006/amd1603-rate-libs-revB/64" The binaries were built with the x86 Open64 Compiler Suite, which is only available from (and supported by) AMD at http://developer.amd.com/tools-and-sdks/cpu-development/x86-open64-compiler-suite/ Base Compiler Invocation ------------------------ C benchmarks: opencc C++ benchmarks: openCC Base Portability Flags ---------------------- 400.perlbench: -DSPEC_CPU_LP64 -DSPEC_CPU_LINUX_X64 401.bzip2: -DSPEC_CPU_LP64 403.gcc: -DSPEC_CPU_LP64 429.mcf: -DSPEC_CPU_LP64 445.gobmk: -DSPEC_CPU_LP64 456.hmmer: -DSPEC_CPU_LP64 458.sjeng: -DSPEC_CPU_LP64 462.libquantum: -DSPEC_CPU_LP64 -DSPEC_CPU_LINUX 464.h264ref: -DSPEC_CPU_LP64 483.xalancbmk: -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -Ofast -CG:local_sched_alg=1 -INLINE:aggressive=ON -IPA:plimit=8000 -IPA:small_pu=100 -HP:bd=2m:heap=2m -mso -LNO:prefetch=2 -march=bdver1 -mno-fma4 -mno-xop -mno-tbm C++ benchmarks: -Ofast -m32 -INLINE:aggressive=on -CG:cmp_peep=on -D__OPEN64_FAST_SET -march=bdver1 -mno-fma4 -mno-xop -mno-tbm -L/root/work/libraries/SmartHeap-10/lib -lsmartheap The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2006/flags/x86-openflags-rate-revA-I.html http://www.spec.org/cpu2006/flags/HPE-Platform-Flags-AMD-V1.2-EPYC-revC.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2006/flags/x86-openflags-rate-revA-I.xml http://www.spec.org/cpu2006/flags/HPE-Platform-Flags-AMD-V1.2-EPYC-revC.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2018 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.2. Report generated on Tue Mar 6 11:48:23 2018 by CPU2006 ASCII formatter v6932. Originally published on 12 December 2017.