SPEC(R) CINT2006 Summary Cisco Systems Cisco UCS C460 M4 (Intel Xeon E7-8890 v3 @ 2.50 GHz) Sun Apr 19 13:42:39 2015 CPU2006 License: 9019 Test date: Apr-2015 Test sponsor: Cisco Systems Hardware availability: Apr-2014 Tested by: Cisco Systems Software availability: Sep-2014 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 144 626 2250 * 400.perlbench 144 626 2250 S 400.perlbench 144 618 2280 S 401.bzip2 144 1004 1380 S 401.bzip2 144 1008 1380 S 401.bzip2 144 1005 1380 * 403.gcc 144 564 2060 S 403.gcc 144 566 2050 S 403.gcc 144 565 2050 * 429.mcf 144 388 3390 * 429.mcf 144 388 3380 S 429.mcf 144 388 3390 S 445.gobmk 144 778 1940 S 445.gobmk 144 782 1930 S 445.gobmk 144 779 1940 * 456.hmmer 144 313 4290 S 456.hmmer 144 316 4250 S 456.hmmer 144 316 4260 * 458.sjeng 144 779 2240 S 458.sjeng 144 779 2240 * 458.sjeng 144 779 2240 S 462.libquantum 144 109 27400 S 462.libquantum 144 109 27400 * 462.libquantum 144 109 27400 S 464.h264ref 144 953 3350 S 464.h264ref 144 955 3340 * 464.h264ref 144 976 3270 S 471.omnetpp 144 725 1240 * 471.omnetpp 144 724 1240 S 471.omnetpp 144 726 1240 S 473.astar 144 661 1530 * 473.astar 144 662 1530 S 473.astar 144 660 1530 S 483.xalancbmk 144 344 2890 S 483.xalancbmk 144 344 2890 * 483.xalancbmk 144 345 2880 S ============================================================================== 400.perlbench 144 626 2250 * 401.bzip2 144 1005 1380 * 403.gcc 144 565 2050 * 429.mcf 144 388 3390 * 445.gobmk 144 779 1940 * 456.hmmer 144 316 4260 * 458.sjeng 144 779 2240 * 462.libquantum 144 109 27400 * 464.h264ref 144 955 3340 * 471.omnetpp 144 725 1240 * 473.astar 144 661 1530 * 483.xalancbmk 144 344 2890 * SPECint(R)_rate_base2006 2770 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon E7-8890 v3 CPU Characteristics: Intel Turbo Boost Technology up to 3.30 GHz CPU MHz: 2500 FPU: Integrated CPU(s) enabled: 72 cores, 4 chips, 18 cores/chip, 2 threads/core CPU(s) orderable: 1,2,3,4 Chip Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 256 KB I+D on chip per core L3 Cache: 45 MB I+D on chip per chip Other Cache: None Memory: 1 TB (64 x 16 GB 2Rx4 PC4-2133P-R, running at 1600 MHz) Disk Subsystem: 1 x 400 GB 6Gb/s SSD Other Hardware: None SOFTWARE -------- Operating System: SUSE Linux Enterprise Server 12 (x86_64) 3.12.28-4-default Compiler: C/C++: Version 15.0.0.090 of Intel C++ Studio XE for Linux Auto Parallel: No File System: xfs System State: Run level 3 (multi-user) Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: Microquill SmartHeap V10.0 Submit Notes ------------ The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" Platform Notes -------------- Power Technology set to Performance CPU Power State C6 set to Disabled CPU Power State C1 Enhanced set to Disabled Package C State Limit set to C0/C1 State Energy Performance policy set to Balanced Performance Memory Power saving mode set to Disabled DRAM Clock Throttling Set to Auto LV DDR Mode set to Performance mode Closed Loop Thermal Throttling set to Enabled Memory RAS configuration set to Maximum Performance Sysinfo program /opt/cpu2006-1.2/config/sysinfo.rev6914 $Rev: 6914 $ $Date:: 2014-06-25 #$ e3fbb8667b5a285932ceab81e28219e1 running on linux-cfac Sun Apr 19 10:42:41 2015 This section contains SUT (System Under Test) info as seen by some common utilities. To remove or add to this section, see: http://www.spec.org/cpu2006/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) CPU E7-8890 v3 @ 2.50GHz 4 "physical id"s (chips) 144 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 18 siblings : 36 physical 0: cores 0 1 2 3 4 8 9 10 11 16 17 18 19 20 24 25 26 27 physical 1: cores 0 1 2 3 4 8 9 10 11 16 17 18 19 20 24 25 26 27 physical 2: cores 0 1 2 3 4 8 9 10 11 16 17 18 19 20 24 25 26 27 physical 3: cores 0 1 2 3 4 8 9 10 11 16 17 18 19 20 24 25 26 27 cache size : 46080 KB From /proc/meminfo MemTotal: 1058822424 kB HugePages_Total: 0 Hugepagesize: 2048 kB From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 0 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12" VERSION_ID="12" PRETTY_NAME="SUSE Linux Enterprise Server 12" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12" uname -a: Linux linux-cfac 3.12.28-4-default #1 SMP Thu Sep 25 17:02:34 UTC 2014 (9879bd4) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Apr 19 02:28 SPEC is set to: /opt/cpu2006-1.2 Filesystem Type Size Used Avail Use% Mounted on /dev/sdq1 xfs 181G 96G 86G 53% / Additional information from dmidecode: Warning: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Cisco Systems, Inc. C460M4.2.0.4.20.040420150215 04/04/2015 Memory: 64x 0xCE00 M393A2G40DB0-CPB 16 GB 2 rank 1600 MHz 32x NO DIMM NO DIMM 1600 MHz (End of data from sysinfo program) General Notes ------------- Environment variables set by runspec before the start of the run: LD_LIBRARY_PATH = "/opt/cpu2006-1.2/libs/32:/opt/cpu2006-1.2/libs/64:/opt/cpu2006-1.2/sh" Binaries compiled on a system with 1x Core i5-4670K CPU + 16GB memory using RedHat EL 7.0 Transparent Huge Pages enabled with: echo always > /sys/kernel/mm/transparent_hugepage/enabled Filesystem page cache cleared with: echo 1> /proc/sys/vm/drop_caches runspec command invoked through numactl i.e.: numactl --interleave=all runspec Base Compiler Invocation ------------------------ C benchmarks: icc -m32 -L/opt/intel/composer_xe_2015/lib/ia32 C++ benchmarks: icpc -m32 -L/opt/intel/composer_xe_2015/lib/ia32 Base Portability Flags ---------------------- 400.perlbench: -DSPEC_CPU_LINUX_IA32 462.libquantum: -DSPEC_CPU_LINUX 483.xalancbmk: -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -opt-prefetch -opt-mem-layout-trans=3 C++ benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -opt-prefetch -opt-mem-layout-trans=3 -Wl,-z,muldefs -L/sh -lsmartheap Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic15.0-official-linux64.html http://www.spec.org/cpu2006/flags/Cisco-Platform-Settings-V1.2-revC.20150505.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2006/flags/Intel-ic15.0-official-linux64.xml http://www.spec.org/cpu2006/flags/Cisco-Platform-Settings-V1.2-revC.20150505.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2015 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.2. Report generated on Tue May 5 15:15:54 2015 by CPU2006 ASCII formatter v6932. Originally published on 5 May 2015.