# Invocation command line: # /SPECcpu2006/bin/runspec -c cpu2006.1.1.ic11.1.linux64.sse42.speed.jan182010.cfg -T all --flagsurl=Intel-ic11.1-linux64-revE.xml -o asc,pdf fp # output_root was not used for this run ############################################################################ ############################################################################ # This is a sample config file. It was tested with: # # Compiler name/version: Intel Compiler 11.1 # Operating system version: 64-Bit SUSE LINUX Enterprise Server 10 or later # Hardware: Intel processors supporting SSE4.2 # ############################################################################ # SPEC CPU2006 Intel Linux64 config file # Sep 2009 Intel Compiler 11.1 for Linux64 ############################################################################ action = validate tune = base ext = cpu2006.1.1.ic11.1.linux64.blm.speed.jan182010 PATHSEP = / check_md5=1 reportable=1 # # These are listed as benchmark-tuning-extension-machine # int=default=default=default: CC= icc -m64 CXX= icpc -m64 OBJ = .o SMARTHEAP32_DIR = /home/cmplr/usr3/alrahate/cpu2006.1.1.ic11.1/libic11.1-32bit SMARTHEAP64_DIR = /home/cmplr/usr3/alrahate/cpu2006.1.1.ic11.1/libic11.1-64bit fp=default=default=default: CC= icc -m64 CXX= icpc -m64 FC= ifort -m64 OBJ = .o #################################################################### # Compiler options # for Nehalem use -xSSE4.2 # for processors prior to dunnington, replace -xSSE4.1 with -xSSSE3 #################################################################### default: SSE = -xSSE4.2 FAST = $(SSE) -ipo -O3 -no-prec-div -static FASTNOSTATIC = $(SSE) -ipo -O3 -no-prec-div ################################################################ # # portability & libraries # #################### Portability Flags and Notes ############################ default: PORTABILITY = -DSPEC_CPU_LP64 400.perlbench=default: CPORTABILITY = -DSPEC_CPU_LINUX_X64 403.gcc=default: EXTRA_CFLAGS= -Dalloca=_alloca 462.libquantum=default: CPORTABILITY= -DSPEC_CPU_LINUX 483.xalancbmk=default=default=default: CXXPORTABILITY= -DSPEC_CPU_LINUX 435.gromacs=default=default=default: LDPORTABILITY = -nofor_main 436.cactusADM=default=default=default: LDPORTABILITY = -nofor_main 454.calculix=default=default=default: LDPORTABILITY = -nofor_main 481.wrf=default=default=default: CPORTABILITY = -DSPEC_CPU_CASE_FLAG -DSPEC_CPU_LINUX ################################################################ # Tuning Flags ################################################################ # Base tuning default optimization # Feedback directed optimization not allowed in baseline for CPU2006 # However there is no limit on the number of flags as long as the same # flags are used in the same order for all benchmarks of a given language ################################################################ 471.omnetpp,473.astar,483.xalancbmk=default: EXTRA_LIBS= -L$(SMARTHEAP64_DIR) -lsmartheap64 EXTRA_LDFLAGS= -Wl,-z,muldefs int=base=default=default: COPTIMIZE= $(FAST) -parallel -opt-prefetch CXXOPTIMIZE= $(FASTNOSTATIC) -opt-prefetch fp=base=default=default: OPTIMIZE= $(FAST) -parallel -opt-prefetch ################################################################ # Peak Tuning Flags int 2006 fast ################################################################ int=peak=default: COPTIMIZE= -auto-ilp32 -ansi-alias CXXOPTIMIZE= -ansi-alas PASS1_CFLAGS = -prof-gen PASS2_CFLAGS = $(FAST) -prof-use PASS1_CXXFLAGS = -prof-gen PASS2_CXXFLAGS = $(FASTNOSTATIC) -prof-use PASS1_LDCFLAGS = -prof-gen PASS2_LDCFLAGS = $(FAST) -prof-use PASS1_LDCXXFLAGS = -prof-gen PASS2_LDCXXFLAGS = $(FASTNOSTATIC) -prof-use 400.perlbench=peak=default: CC= icc -m32 PORTABILITY= CPORTABILITY = -DSPEC_CPU_LINUX_IA32 COPTIMIZE= -ansi-alias -opt-prefetch 401.bzip2=peak=default: COPTIMIZE= -auto-ilp32 -opt-prefetch -ansi-alias -no-prec-div 403.gcc=peak=default: COPTIMIZE= $(FAST) -inline-calloc -opt-malloc-options=3 -auto-ilp32 feedback=0 429.mcf=peak=default: CC= icc -m32 PORTABILITY= COPTIMIZE= $(FAST) -opt-prefetch feedback=0 445.gobmk=peak=default: CC= icc -m32 PORTABILITY= COPTIMIZE= -O2 -ipo -no-prec-div -ansi-alias PASS1_CFLAGS = -prof-gen PASS2_CFLAGS = $(SSE) -prof-use PASS1_LDCFLAGS = -prof-gen PASS2_LDCFLAGS = $(SSE) -prof-use 456.hmmer=peak=default: COPTIMIZE= $(FAST) -unroll2 -ansi-alias -auto-ilp32 feedback=0 458.sjeng=peak=default: COPTIMIZE= -unroll4 462.libquantum=peak=default: COPTIMIZE= $(FAST) -parallel -opt-prefetch -par-schedule-static=32768 -ansi-alias feedback=0 464.h264ref=peak=default: CC= icc -m32 PORTABILITY= COPTIMIZE= -unroll2 -ansi-alias 471.omnetpp=peak=default: CXX= icpc -m32 EXTRA_LIBS= -L$(SMARTHEAP32_DIR) -lsmartheap PORTABILITY= CXXOPTIMIZE= -ansi-alias -opt-ra-region-strategy=block 473.astar=peak=default: CXXOPTIMIZE= -ansi-alias -opt-ra-region-strategy=routine 483.xalancbmk=peak=default: CXX= icpc -m32 EXTRA_LIBS= -L$(SMARTHEAP32_DIR) -lsmartheap PORTABILITY= CXXOPTIMIZE= $(FASTNOSTATIC) -opt-prefetch feedback=no ################################################################ # Peak Tuning Flags for FP ################################################################ fp=peak=default: COPTIMIZE= -auto-ilp32 CXXOPTIMIZE= -auto-ilp32 PASS1_CFLAGS = -prof-gen PASS2_CFLAGS = $(FAST) -prof-use PASS1_CXXFLAGS = -prof-gen PASS2_CXXFLAGS = $(FAST) -prof-use PASS1_FFLAGS = -prof-gen PASS2_FFLAGS = $(FAST) -prof-use PASS1_LDFLAGS = -prof-gen PASS2_LDFLAGS = $(FAST) -prof-use 410.bwaves=peak=default: OPTIMIZE= $(FAST) -opt-prefetch -parallel feedback=0 416.gamess=peak=default: OPTIMIZE= -unroll2 -Ob0 -ansi-alias -scalar-rep- 433.milc=peak=default: OPTIMIZE= -ansi-alias COPTIMIZE= 434.zeusmp=peak=default: basepeak=yes 435.gromacs=peak=default: OPTIMIZE= -opt-prefetch 436.cactusADM=peak=default: OPTIMIZE= -unroll2 -opt-prefetch -parallel 437.leslie3d=peak=default: basepeak=yes 444.namd=peak=default: OPTIMIZE= -fno-alias 447.dealII=peak=default: OPTIMIZE= -unroll2 -ansi-alias -scalar-rep- 450.soplex=peak=default: OPTIMIZE= -opt-malloc-options=3 453.povray=peak=default: CXXOPTIMIZE= -unroll4 -ansi-alias 454.calculix=peak=default: OPTIMIZE= $(FAST) feedback=0 459.GemsFDTD=peak=default: OPTIMIZE= -unroll2 -Ob0 -opt-prefetch -parallel 465.tonto=peak=default: OPTIMIZE= -inline-calloc -opt-malloc-options=3 -auto -unroll4 470.lbm=peak=default: OPTIMIZE= -parallel -ansi-alias 481.wrf=peak=default: OPTIMIZE= $(FAST) feedback=0 482.sphinx3=peak=default: OPTIMIZE= $(FAST) COPTIMIZE= -auto-ilp32 -unroll2 feedback=no #include: SUT-speed.conf # ----- Begin inclusion of 'SUT-speed.conf' ############################################################################ ################################################################# # (Edit this to match your system) ################################################################# default=default=default=default: license_num = 19 test_sponsor = Fujitsu hw_avail = Jul-2010 sw_avail = Jan-2010 tester = Fujitsu hw_disk = 1 x SATA, 160 GB, 5.4 krpm hw_fpu = Integrated hw_other = None hw_vendor = Fujitsu hw_ncpuorder = 1,2 chips hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) sw_file = ext3 sw_os000 = SUSE Linux Enterprise Server 11 (x86_64), sw_os001 = Kernel 2.6.27.19-5-default sw_state = Multi-User Run Level 3 %ifdef %{no-numa) notes_submit_000 = taskset was used to bind copies to the cores %endif notes_os_000= 'ulimit -s unlimited' was used to set the stacksize to unlimited prior to run notes_plat_005= BIOS configuration: notes_plat_010= Data Reuse Optimization = Disable notes_015 = For information about Fujitsu please visit: http://www.fujitsu.com #BEGIN E5503 hw_cpu_name = Intel Xeon E5503 hw_cpu_char = hw_cpu_char = hw_cpu_mhz = 2000 hw_memory000 = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, hw_memory001 = see add'l detail in notes) #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) hw_model = PRIMERGY TX200 S6, Intel Xeon E5503, 2.0 GHz hw_ncores = 4 hw_nchips = 2 hw_ncoresperchip = 2 hw_nthreadspercore = 1 hw_pcache = 32 KB I + 32 KB D on chip per core hw_scache = 256 KB I+D on chip per core hw_tcache = 4 MB I+D on chip per chip hw_ocache = None prepared_by = Peter Klassen notes_plat_000 = The system automatically configures the memory to run at 800 MHz. #END E5503 #BEGIN E5506 #hw_cpu_name = Intel Xeon E5506 #hw_cpu_char = #hw_cpu_mhz = 2133 #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon E5506, 2.13 GHz #hw_ncores = 8 #hw_nchips = 2 #hw_ncoresperchip = 4 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 4 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen #notes_plat_000 = The system automatically configures the memory to run at 800 MHz. #END E5506 #BEGIN E5507 #hw_cpu_name = Intel Xeon E5507 ##hw_cpu_char = ##hw_cpu_char = #hw_cpu_mhz = 2267 #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon E5507, 2.26 GHz #hw_ncores = 8 #hw_nchips = 2 #hw_ncoresperchip = 4 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 4 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen #notes_plat_000 = The system automatically configures the memory to run at 800 MHz. #END E5507 #BEGIN E5620 #hw_cpu_name = Intel Xeon E5620 #hw_cpu_char = Intel Turbo Boost Technology up to 2.66 GHz ##hw_cpu_char = #hw_cpu_mhz = 2400 #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon E5620, 2.40 GHz #hw_ncores = 8 #hw_nchips = 2 #hw_ncoresperchip = 4 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 12 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen #notes_plat_000 = The system automatically configures the memory to run at 1066 MHz. #notes_plat030 = Intel HT Technology = Disable #END E5620 #BEGIN E5630 #hw_cpu_name = Intel Xeon E5630 #hw_cpu_char = Intel Turbo Boost Technology up to 2.8 GHz ##hw_cpu_char = #hw_cpu_mhz = 2533 #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon E5630, 2.53 GHz #hw_ncores = 8 #hw_nchips = 2 #hw_ncoresperchip = 4 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 12 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen #notes_plat_000 = The system automatically configures the memory to run at 1066 MHz. #notes_plat030 = Intel HT Technology = Disable #END E5630 #BEGIN E5640 #hw_cpu_name = Intel Xeon E5640 ##hw_cpu_char = Intel Turbo Boost Technology up to 2.93 GHz ###hw_cpu_char = #hw_cpu_mhz = 2667 #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon E5640, 2.66 GHz #hw_ncores = 8 #hw_nchips = 2 #hw_ncoresperchip = 4 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 12 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen #notes_plat_000 = The system automatically configures the memory to run at 1066 MHz. #notes_plat030 = Intel HT Technology = Disable #END E5630 #BEGIN L5609 #hw_cpu_name = Intel Xeon L5609 ##hw_cpu_char = Intel Turbo Boost Technology up to 2.93 GHz ##hw_cpu_char = #hw_cpu_mhz = 1867 #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon L5609, 1.86 GHz #hw_ncores = 8 #hw_nchips = 2 #hw_ncoresperchip = 4 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 12 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen #notes_plat_000 = The system automatically configures the memory to run at 1066 MHz. #END L5609 #BEGIN L5630 #hw_cpu_name = Intel Xeon L5630 #hw_cpu_char = Intel Turbo Boost Technology up to 2.4 GHz ##hw_cpu_char = #hw_cpu_mhz = 2133 #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon L5630, 2.13 GHz #hw_ncores = 8 #hw_nchips = 2 #hw_ncoresperchip = 4 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 12 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen #notes_plat_000 = The system automatically configures the memory to run at 1066 MHz. #notes_plat030 = Intel HT Technology = Disable #END L5630 #BEGIN L5640 #hw_cpu_name = Intel Xeon L5640 #hw_cpu_char = Intel Turbo Boost Technology up to 2.8 GHz ##hw_cpu_char = #hw_cpu_mhz = 2267 ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon L5640, 2.26 GHz #hw_ncores = 12 #hw_nchips = 2 #hw_ncoresperchip = 6 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 12 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen ##notes_plat_000 = The system automatically configures the memory to run at 1066 MHz. #notes_plat030 = Intel HT Technology = Disable #END L5640 #BEGIN X5650 #hw_cpu_name = Intel Xeon X5650 #hw_cpu_char = Intel Turbo Boost Technology up to 3.06 GHz ##hw_cpu_char = #hw_cpu_mhz = 2667 ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon X5650, 2.66 GHz #hw_ncores = 12 #hw_nchips = 2 #hw_ncoresperchip = 6 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 12 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen ##notes_plat_000 = The system automatically configures the memory to run at 1066 MHz. #notes_plat030 = Intel HT Technology = Disable #END X5650 #BEGIN X5660 #hw_cpu_name = Intel Xeon X5660 #hw_cpu_char = Intel Turbo Boost Technology up to 3.2 GHz ##hw_cpu_char = #hw_cpu_mhz = 2800 ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon X5660, 2.80 GHz #hw_ncores = 12 #hw_nchips = 2 #hw_ncoresperchip = 6 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 12 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen ##notes_plat_000 = The system automatically configures the memory to run at 1066 MHz. #notes_plat030 = Intel HT Technology = Disable #END X5660 #BEGIN X5670 #hw_cpu_name = Intel Xeon X5670 #hw_cpu_char = Intel Turbo Boost Technology up to 3.33 GHz ##hw_cpu_char = #hw_cpu_mhz = 2933 ##hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC, see add'l detail in notes) #hw_memory = 48 GB (12x4 GB PC3-10600R, 2 rank, CL9-9-9, ECC) #hw_model = PRIMERGY TX200 S6, Intel Xeon X5670, 2.93 GHz #hw_ncores = 12 #hw_nchips = 2 #hw_ncoresperchip = 6 #hw_nthreadspercore = 1 #hw_pcache = 32 KB I + 32 KB D on chip per core #hw_scache = 256 KB I+D on chip per core #hw_tcache = 12 MB I+D on chip per chip #hw_ocache = None #prepared_by = Peter Klassen ##notes_plat_000 = The system automatically configures the memory to run at 1066 MHz. #notes_plat030 = Intel HT Technology = Disable #END X5670 int=default=default=default: sw_compiler001 = Intel C++ Professional Compiler for IA32 and Intel 64, Version 11.1 sw_compiler002 = Build 20091130 Package ID: l_cproc_p_11.1.064 sw_base_ptrsize = 64-bit sw_peak_ptrsize = 32/64-bit notes_028 = OMP_NUM_THREADS set to number of cores notes_029 = KMP_AFFINITY set to granularity=fine,scatter sw_other = Microquill SmartHeap V8.1 fp=default=default=default: sw_compiler000 = Intel C++ and Fortran Professional Compiler for sw_compiler001 = IA32 and Intel 64, Version 11.1 sw_compiler002 = Build 20091130 Package ID: l_cproc_p_11.1.064, sw_compiler003 = l_cprof_p_11.1.064 sw_base_ptrsize = 64-bit sw_peak_ptrsize = 32/64-bit notes_000 = OMP_NUM_THREADS set to number of cores notes_005 = KMP_AFFINITY set to granularity=fine,scatter notes_010 = KMP_STACKSIZE set to 200M sw_other = None # ---- End inclusion of '/SPECcpu2006/config/SUT-speed.conf' # The following section was added automatically, and contains settings that # did not appear in the original configuration file, but were added to the # raw file after the run. 470.lbm: # The following setting was inserted automatically as a result of # post-run basepeak application. basepeak = 1 444.namd: # The following setting was inserted automatically as a result of # post-run basepeak application. basepeak = 1 default: flagsurl000 = http://www.spec.org/cpu2006/flags/Intel-ic11.1-linux64-revE.20100708.xml