CPU2006 Flag Description
Dell Inc. PowerEdge R410 (Intel Xeon E5502, 1.86 GHz)

Base Optimization Flags

C benchmarks

• • -QxSSE4.2
  • 
  • OPTIMIZE

  • Tells the compiler to generate optimized code specialized for the Intel processor that executes your program.
    Syntax -Qx(processor)

    (processor)indicates the processor for which code is generated. Many of the following descriptions refer to Intel® Streaming SIMD Extensions

    Host
    Can generate instructions for the highest instruction set available on the compilation host processor.
    On Intel processors, this may correspond to the most suitable –x (Linux* and Mac OS* X) or /Qx (Windows*) option. On non-Intel processors, this may correspond to the most suitable –m (Linux and Mac OS X) or /arch (Windows) option. The resulting executable may not run on a processor different from the host in the following cases:
    If the processor does not support all of the instructions supported by the host processor.
    If the host is an Intel processor and the other processor is a non-Intel processor.

    AVX
    Optimizes for Intel processors that support Intel® Advanced Vector Extensions (Intel® AVX).

    SSE4.2
    Can generate Intel® SSE4 Efficient Accelerated String and Text Processing instructions supported by Intel® Core™ i7 processors. Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator, Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for the Intel® Core™ processor family.

    SSE4.1
    Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator instructions for Intel processors. Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for Intel® 45nm Hi-k next generation Intel® Core™ microarchitecture. This replaces value S, which is deprecated.

    SSE3_ATOM
    Optimizes for the Intel® Atom™ processor and Intel® Centrino® Atom™ Processor Technology. Can generate MOVBE instructions, depending on the setting of option -minstruction (Linux and Mac OS) or /Qinstruction (Windows).

    SSSE3
    Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for the Intel® Core™2 Duo processor family. For Mac OS* X systems, this value is only supported on Intel® 64 architecture. This replaces value T, which is deprecated.

    SSE3
    Can generate Intel® SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for processors based on Intel® Core™ microarchitecture and Intel NetBurst® microarchitecture. For Mac OS* X systems, this value is only supported on IA-32 architecture.This replaces value P, which is deprecated.

    SSE2
    Can generate Intel® SSE2 and SSE instructions for Intel processors, and it can optimize for Intel® Pentium® 4 processors, Intel® Pentium® M processors, and Intel® Xeon® processors with Intel® SSE2. This value is not available on Mac OS* X systems. This replaces value N, which is deprecated.

    Default
    Windows systems: None
    Linux systems: None
    Mac OS X systems using IA-32 architecture: SSE3
    Mac OS X systems using Intel® 64 architecture: SSSE3
    On Windows systems, if neither /Qx nor /arch is specified, the default is /arch:SSE2.
    On Linux systems, if neither -x nor -m is specified, the default is -msse2.

    Description
    This option tells the compiler to generate optimized code specialized for the Intel processor that executes your program. It also enables optimizations in addition to Intel processor-specific optimizations. The specialized code generated by this option may run only on a subset of Intel processors.

    This option can enable optimizations depending on the argument specified. For example, it may enable Intel® Streaming SIMD Extensions 4 (Intel® SSE4), Intel® Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3), Intel® Streaming SIMD Extensions 3 (Intel® SSE3), Intel® Streaming SIMD Extensions 2 (Intel® SSE2), or Intel® Streaming SIMD Extensions (Intel® SSE) instructions.

    The binaries produced by these values will run on Intel processors that support all of the features for the targeted processor. For example, binaries produced with SSE3 will run on an Intel® Core™ 2 Duo processor, because that processor completely supports all of the capabilities of the Intel® Pentium® 4 processor, which the SSE3 value targets. Specifying the SSSE3 value has the potential of using more features and optimizations available to the Intel® Core™ 2 Duo processor.

    Do not use processor values to create binaries that will execute on a processor that is not compatible with the targeted processor. The resulting program may fail with an illegal instruction exception or display other unexpected behavior. For example, binaries produced with SSE3 may produce code that will not run on Intel® Pentium® III processors or earlier processors that do not support SSE3 instructions.

    Compiling the function main() with any of the processor values produces binaries that display a fatal run-time error if they are executed on unsupported processors. For more information, see Optimizing Applications.

    If you specify more than one processor value, code is generated for only the highest-performing processor specified. The highest-performing to lowest-performing processor values are: SSE4.2, SSE4.1, SSSE3, SSE3, SSE2.Note that processor values AVX and SSE3_ATOM do not fit within this group.

    Compiler options m and arch produce binaries that should run on processors not made by Intel that implement the same capabilities as the corresponding Intel processors.

    Previous value O is deprecated and has been replaced by option -msse3 (Linux and Mac OS X) and option /arch:SSE3 (Windows).

    Previous values W and K are deprecated. The details on replacements are as follows:

    • Mac OS X systems: On these systems, there is no exact replacement for W or K. You can upgrade to the default option -msse3 (IA-32 architecture) or option -mssse3 (Intel® 64 architecture).
    • Windows and Linux systems: The replacement for W is -msse2 (Linux) or /arch:SSE2 (Windows).

    There is no exact replacement for K. However, on Windows systems, /QxK is interpreted as /arch:IA32; on Linux systems, -xK is interpreted as -mia32. You can also do one of the following:

    • Upgrade to option -msse2 (Linux) or option /arch:SSE2 (Windows). This will produce one code path that is specialized for Intel® SSE2. It will not run on earlier processors.
    • Specify the two option combination -mia32 -axSSE2 (Linux) or /arch:IA32 /QaxSSE2 (Windows). This combination will produce an executable that runs on any processor with IA-32 architecture but with an additional specialized Intel® SSE2 code path.

    The -x and /Qx options enable additional optimizations not enabled with option -m or option /arch.

    On Windows* systems, options /Qx and /arch are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning. Similarly, on Linux* and Mac OS* X systems, options -x and -m are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning.

• • -Qauto-ilp32
  • 
  • OPTIMIZE

  • This option instructs the compiler to analyze and transform the program so that 64-bit pointers are shrunk to 32-bit pointers, and 64-bit longs (on Linux) are shrunk into 32-bit longs wherever it is legal and safe to do so. In order for this option to be effective the compiler must be able to optimize using the -ipo/-Qipo option and must be able to analyze all library/external calls the program makes.

    This option requires that the size of the program executable never exceeds 2**32 bytes and all data values can be represented within 32 bits. If the program can run correctly in a 32-bit system, these requirements are implicitly satisfied. If the program violates these size restrictions, unpredictable behavior might occur.

• • -Qipo
  • 
  • OPTIMIZE

  • Multi-file ip optimizations that includes:
    - inline function expansion
    - interprocedural constant propogation
    - dead code elimination
    - propagation of function characteristics
    - passing arguments in registers
    - loop-invariant code motion

• • -O3
  • 
  • OPTIMIZE

  • Enables O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enables optimizations for maximum speed, such as:

    • Loop unrolling, including instruction scheduling
    • Code replication to eliminate branches
    • Padding the size of certain power-of-two arrays to allow more efficient cache use.

    On Windows systems, the O3 option sets the /GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2 option.

    On Linux and Mac OS X systems, the O3 option sets option -fomit-frame-pointer.

    On systems using IA-32 architecture or Intel64 architecture, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times.

    On systems using IA-64 architecture, the O3 option enables optimizations for technical computing applications (loop-intensive code): loop\ optimizations and data prefetch.

    The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations.
    The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.

  • Includes:
    • -GF
    • -Gf
    • -Ob_n
    • -O2
      • -Oi-
      • -Gs
      • -Oy
      • -Gy
      • -Os
      • -GF
      • -Gf
      • -Ob_n
      • -Og
      • -O1
        • -Qunroll_n
        • -Oi-
        • -Op-
        • -Oy
        • -Gy
        • -Os
        • -GF
        • -Gf
        • -Ob_n
        • -Og
• • -Qprec-div-
  • 
  • OPTIMIZE

  • This option improves precision of floating-point divides. It has a slight impact on speed.

    With some optimizations, such as -xSSE2 (Linux) or /QxSSE2 (Windows), the compiler may change floating-point division computations into multiplication by the reciprocal of the denominator. For example, A/B is computed as A * (1/B) to improve the speed of the computation.

    However, sometimes the value produced by this transformation is not as accurate as full IEEE division. When it is important to have fully precise IEEE division, use this option to disable the floating-point division-to-multiplication optimization. The result is more accurate, with some loss of performance.

    If you specify -no-prec-div (Linux and Mac OS X) or /Qprec-div- (Windows), it enables optimizations that give slightly less precise results than full IEEE division.

    Default: -prec-div or/Qprec-div

• • -Qparallel
  • 
  • Yes
  • OPTIMIZE

  • This option tells the auto-parallelizer to generate multithreaded code for loops that can be safely executed in parallel.
    To use this option, you must also specify option O2 or O3.

• • -Qopt-prefetch
  • 
  • OPTIMIZE

  • This option enables or disables prefetch insertion optimization. The goal of prefetching is to reduce cache misses by providing hints to the processor about when data should be loaded into the cache.

    On IA-32 architecture and Intel 64 architecture, this option enables prefetching when higher optimization levels are specified.

• • /F512000000
  • 
  • EXTRA_LDFLAGS

  • set the stack reserve amount specified to the linker.

C++ benchmarks

• • -QxSSE4.2
  • 
  • OPTIMIZE

  • Tells the compiler to generate optimized code specialized for the Intel processor that executes your program.
    Syntax -Qx(processor)

    (processor)indicates the processor for which code is generated. Many of the following descriptions refer to Intel® Streaming SIMD Extensions

    Host
    Can generate instructions for the highest instruction set available on the compilation host processor.
    On Intel processors, this may correspond to the most suitable –x (Linux* and Mac OS* X) or /Qx (Windows*) option. On non-Intel processors, this may correspond to the most suitable –m (Linux and Mac OS X) or /arch (Windows) option. The resulting executable may not run on a processor different from the host in the following cases:
    If the processor does not support all of the instructions supported by the host processor.
    If the host is an Intel processor and the other processor is a non-Intel processor.

    AVX
    Optimizes for Intel processors that support Intel® Advanced Vector Extensions (Intel® AVX).

    SSE4.2
    Can generate Intel® SSE4 Efficient Accelerated String and Text Processing instructions supported by Intel® Core™ i7 processors. Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator, Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for the Intel® Core™ processor family.

    SSE4.1
    Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator instructions for Intel processors. Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for Intel® 45nm Hi-k next generation Intel® Core™ microarchitecture. This replaces value S, which is deprecated.

    SSE3_ATOM
    Optimizes for the Intel® Atom™ processor and Intel® Centrino® Atom™ Processor Technology. Can generate MOVBE instructions, depending on the setting of option -minstruction (Linux and Mac OS) or /Qinstruction (Windows).

    SSSE3
    Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for the Intel® Core™2 Duo processor family. For Mac OS* X systems, this value is only supported on Intel® 64 architecture. This replaces value T, which is deprecated.

    SSE3
    Can generate Intel® SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for processors based on Intel® Core™ microarchitecture and Intel NetBurst® microarchitecture. For Mac OS* X systems, this value is only supported on IA-32 architecture.This replaces value P, which is deprecated.

    SSE2
    Can generate Intel® SSE2 and SSE instructions for Intel processors, and it can optimize for Intel® Pentium® 4 processors, Intel® Pentium® M processors, and Intel® Xeon® processors with Intel® SSE2. This value is not available on Mac OS* X systems. This replaces value N, which is deprecated.

    Default
    Windows systems: None
    Linux systems: None
    Mac OS X systems using IA-32 architecture: SSE3
    Mac OS X systems using Intel® 64 architecture: SSSE3
    On Windows systems, if neither /Qx nor /arch is specified, the default is /arch:SSE2.
    On Linux systems, if neither -x nor -m is specified, the default is -msse2.

    Description
    This option tells the compiler to generate optimized code specialized for the Intel processor that executes your program. It also enables optimizations in addition to Intel processor-specific optimizations. The specialized code generated by this option may run only on a subset of Intel processors.

    This option can enable optimizations depending on the argument specified. For example, it may enable Intel® Streaming SIMD Extensions 4 (Intel® SSE4), Intel® Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3), Intel® Streaming SIMD Extensions 3 (Intel® SSE3), Intel® Streaming SIMD Extensions 2 (Intel® SSE2), or Intel® Streaming SIMD Extensions (Intel® SSE) instructions.

    The binaries produced by these values will run on Intel processors that support all of the features for the targeted processor. For example, binaries produced with SSE3 will run on an Intel® Core™ 2 Duo processor, because that processor completely supports all of the capabilities of the Intel® Pentium® 4 processor, which the SSE3 value targets. Specifying the SSSE3 value has the potential of using more features and optimizations available to the Intel® Core™ 2 Duo processor.

    Do not use processor values to create binaries that will execute on a processor that is not compatible with the targeted processor. The resulting program may fail with an illegal instruction exception or display other unexpected behavior. For example, binaries produced with SSE3 may produce code that will not run on Intel® Pentium® III processors or earlier processors that do not support SSE3 instructions.

    Compiling the function main() with any of the processor values produces binaries that display a fatal run-time error if they are executed on unsupported processors. For more information, see Optimizing Applications.

    If you specify more than one processor value, code is generated for only the highest-performing processor specified. The highest-performing to lowest-performing processor values are: SSE4.2, SSE4.1, SSSE3, SSE3, SSE2.Note that processor values AVX and SSE3_ATOM do not fit within this group.

    Compiler options m and arch produce binaries that should run on processors not made by Intel that implement the same capabilities as the corresponding Intel processors.

    Previous value O is deprecated and has been replaced by option -msse3 (Linux and Mac OS X) and option /arch:SSE3 (Windows).

    Previous values W and K are deprecated. The details on replacements are as follows:

    • Mac OS X systems: On these systems, there is no exact replacement for W or K. You can upgrade to the default option -msse3 (IA-32 architecture) or option -mssse3 (Intel® 64 architecture).
    • Windows and Linux systems: The replacement for W is -msse2 (Linux) or /arch:SSE2 (Windows).

    There is no exact replacement for K. However, on Windows systems, /QxK is interpreted as /arch:IA32; on Linux systems, -xK is interpreted as -mia32. You can also do one of the following:

    • Upgrade to option -msse2 (Linux) or option /arch:SSE2 (Windows). This will produce one code path that is specialized for Intel® SSE2. It will not run on earlier processors.
    • Specify the two option combination -mia32 -axSSE2 (Linux) or /arch:IA32 /QaxSSE2 (Windows). This combination will produce an executable that runs on any processor with IA-32 architecture but with an additional specialized Intel® SSE2 code path.

    The -x and /Qx options enable additional optimizations not enabled with option -m or option /arch.

    On Windows* systems, options /Qx and /arch are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning. Similarly, on Linux* and Mac OS* X systems, options -x and -m are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning.

• • -Qauto-ilp32
  • 
  • OPTIMIZE

  • This option instructs the compiler to analyze and transform the program so that 64-bit pointers are shrunk to 32-bit pointers, and 64-bit longs (on Linux) are shrunk into 32-bit longs wherever it is legal and safe to do so. In order for this option to be effective the compiler must be able to optimize using the -ipo/-Qipo option and must be able to analyze all library/external calls the program makes.

    This option requires that the size of the program executable never exceeds 2**32 bytes and all data values can be represented within 32 bits. If the program can run correctly in a 32-bit system, these requirements are implicitly satisfied. If the program violates these size restrictions, unpredictable behavior might occur.

• • -Qipo
  • 
  • OPTIMIZE

  • Multi-file ip optimizations that includes:
    - inline function expansion
    - interprocedural constant propogation
    - dead code elimination
    - propagation of function characteristics
    - passing arguments in registers
    - loop-invariant code motion

• • -O3
  • 
  • OPTIMIZE

  • Enables O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enables optimizations for maximum speed, such as:

    • Loop unrolling, including instruction scheduling
    • Code replication to eliminate branches
    • Padding the size of certain power-of-two arrays to allow more efficient cache use.

    On Windows systems, the O3 option sets the /GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2 option.

    On Linux and Mac OS X systems, the O3 option sets option -fomit-frame-pointer.

    On systems using IA-32 architecture or Intel64 architecture, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times.

    On systems using IA-64 architecture, the O3 option enables optimizations for technical computing applications (loop-intensive code): loop\ optimizations and data prefetch.

    The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations.
    The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.

  • Includes:
    • -GF
    • -Gf
    • -Ob_n
    • -O2
      • -Oi-
      • -Gs
      • -Oy
      • -Gy
      • -Os
      • -GF
      • -Gf
      • -Ob_n
      • -Og
      • -O1
        • -Qunroll_n
        • -Oi-
        • -Op-
        • -Oy
        • -Gy
        • -Os
        • -GF
        • -Gf
        • -Ob_n
        • -Og
• • -Qprec-div-
  • 
  • OPTIMIZE

  • This option improves precision of floating-point divides. It has a slight impact on speed.

    With some optimizations, such as -xSSE2 (Linux) or /QxSSE2 (Windows), the compiler may change floating-point division computations into multiplication by the reciprocal of the denominator. For example, A/B is computed as A * (1/B) to improve the speed of the computation.

    However, sometimes the value produced by this transformation is not as accurate as full IEEE division. When it is important to have fully precise IEEE division, use this option to disable the floating-point division-to-multiplication optimization. The result is more accurate, with some loss of performance.

    If you specify -no-prec-div (Linux and Mac OS X) or /Qprec-div- (Windows), it enables optimizations that give slightly less precise results than full IEEE division.

    Default: -prec-div or/Qprec-div

• • -Qparallel
  • 
  • Yes
  • OPTIMIZE

  • This option tells the auto-parallelizer to generate multithreaded code for loops that can be safely executed in parallel.
    To use this option, you must also specify option O2 or O3.

• • -Qopt-prefetch
  • 
  • OPTIMIZE

  • This option enables or disables prefetch insertion optimization. The goal of prefetching is to reduce cache misses by providing hints to the processor about when data should be loaded into the cache.

    On IA-32 architecture and Intel 64 architecture, this option enables prefetching when higher optimization levels are specified.

• • -Qcxx_features
  • 
  • CXXOPTIMIZE

  • Enable C++ Exception Handling and RTTI
    This option has the same effect as specifying /GX /GR.

  • Includes:
    • -GX
    • -GR
• • /F512000000
  • 
  • EXTRA_LDFLAGS

  • set the stack reserve amount specified to the linker.

• • shlw64mt.lib
  • 
  • EXTRA_LIBS

  • 64-bit MicroQuill SmartHeap Library 8.0 for Windows available from http://www.microquill.com/
    This library is the thread-safe version.

• • -link /FORCE:MULTIPLE
  • 
  • LDOUT

  • Enable SmartHeap library usage by forcing the linker to ignore multiple definitions

Fortran benchmarks

• • -QxSSE4.2
  • 
  • OPTIMIZE

  • Tells the compiler to generate optimized code specialized for the Intel processor that executes your program.
    Syntax -Qx(processor)

    (processor)indicates the processor for which code is generated. Many of the following descriptions refer to Intel® Streaming SIMD Extensions

    Host
    Can generate instructions for the highest instruction set available on the compilation host processor.
    On Intel processors, this may correspond to the most suitable –x (Linux* and Mac OS* X) or /Qx (Windows*) option. On non-Intel processors, this may correspond to the most suitable –m (Linux and Mac OS X) or /arch (Windows) option. The resulting executable may not run on a processor different from the host in the following cases:
    If the processor does not support all of the instructions supported by the host processor.
    If the host is an Intel processor and the other processor is a non-Intel processor.

    AVX
    Optimizes for Intel processors that support Intel® Advanced Vector Extensions (Intel® AVX).

    SSE4.2
    Can generate Intel® SSE4 Efficient Accelerated String and Text Processing instructions supported by Intel® Core™ i7 processors. Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator, Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for the Intel® Core™ processor family.

    SSE4.1
    Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator instructions for Intel processors. Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for Intel® 45nm Hi-k next generation Intel® Core™ microarchitecture. This replaces value S, which is deprecated.

    SSE3_ATOM
    Optimizes for the Intel® Atom™ processor and Intel® Centrino® Atom™ Processor Technology. Can generate MOVBE instructions, depending on the setting of option -minstruction (Linux and Mac OS) or /Qinstruction (Windows).

    SSSE3
    Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for the Intel® Core™2 Duo processor family. For Mac OS* X systems, this value is only supported on Intel® 64 architecture. This replaces value T, which is deprecated.

    SSE3
    Can generate Intel® SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for processors based on Intel® Core™ microarchitecture and Intel NetBurst® microarchitecture. For Mac OS* X systems, this value is only supported on IA-32 architecture.This replaces value P, which is deprecated.

    SSE2
    Can generate Intel® SSE2 and SSE instructions for Intel processors, and it can optimize for Intel® Pentium® 4 processors, Intel® Pentium® M processors, and Intel® Xeon® processors with Intel® SSE2. This value is not available on Mac OS* X systems. This replaces value N, which is deprecated.

    Default
    Windows systems: None
    Linux systems: None
    Mac OS X systems using IA-32 architecture: SSE3
    Mac OS X systems using Intel® 64 architecture: SSSE3
    On Windows systems, if neither /Qx nor /arch is specified, the default is /arch:SSE2.
    On Linux systems, if neither -x nor -m is specified, the default is -msse2.

    Description
    This option tells the compiler to generate optimized code specialized for the Intel processor that executes your program. It also enables optimizations in addition to Intel processor-specific optimizations. The specialized code generated by this option may run only on a subset of Intel processors.

    This option can enable optimizations depending on the argument specified. For example, it may enable Intel® Streaming SIMD Extensions 4 (Intel® SSE4), Intel® Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3), Intel® Streaming SIMD Extensions 3 (Intel® SSE3), Intel® Streaming SIMD Extensions 2 (Intel® SSE2), or Intel® Streaming SIMD Extensions (Intel® SSE) instructions.

    The binaries produced by these values will run on Intel processors that support all of the features for the targeted processor. For example, binaries produced with SSE3 will run on an Intel® Core™ 2 Duo processor, because that processor completely supports all of the capabilities of the Intel® Pentium® 4 processor, which the SSE3 value targets. Specifying the SSSE3 value has the potential of using more features and optimizations available to the Intel® Core™ 2 Duo processor.

    Do not use processor values to create binaries that will execute on a processor that is not compatible with the targeted processor. The resulting program may fail with an illegal instruction exception or display other unexpected behavior. For example, binaries produced with SSE3 may produce code that will not run on Intel® Pentium® III processors or earlier processors that do not support SSE3 instructions.

    Compiling the function main() with any of the processor values produces binaries that display a fatal run-time error if they are executed on unsupported processors. For more information, see Optimizing Applications.

    If you specify more than one processor value, code is generated for only the highest-performing processor specified. The highest-performing to lowest-performing processor values are: SSE4.2, SSE4.1, SSSE3, SSE3, SSE2.Note that processor values AVX and SSE3_ATOM do not fit within this group.

    Compiler options m and arch produce binaries that should run on processors not made by Intel that implement the same capabilities as the corresponding Intel processors.

    Previous value O is deprecated and has been replaced by option -msse3 (Linux and Mac OS X) and option /arch:SSE3 (Windows).

    Previous values W and K are deprecated. The details on replacements are as follows:

    • Mac OS X systems: On these systems, there is no exact replacement for W or K. You can upgrade to the default option -msse3 (IA-32 architecture) or option -mssse3 (Intel® 64 architecture).
    • Windows and Linux systems: The replacement for W is -msse2 (Linux) or /arch:SSE2 (Windows).

    There is no exact replacement for K. However, on Windows systems, /QxK is interpreted as /arch:IA32; on Linux systems, -xK is interpreted as -mia32. You can also do one of the following:

    • Upgrade to option -msse2 (Linux) or option /arch:SSE2 (Windows). This will produce one code path that is specialized for Intel® SSE2. It will not run on earlier processors.
    • Specify the two option combination -mia32 -axSSE2 (Linux) or /arch:IA32 /QaxSSE2 (Windows). This combination will produce an executable that runs on any processor with IA-32 architecture but with an additional specialized Intel® SSE2 code path.

    The -x and /Qx options enable additional optimizations not enabled with option -m or option /arch.

    On Windows* systems, options /Qx and /arch are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning. Similarly, on Linux* and Mac OS* X systems, options -x and -m are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning.

• • -Qauto-ilp32
  • 
  • OPTIMIZE

  • This option instructs the compiler to analyze and transform the program so that 64-bit pointers are shrunk to 32-bit pointers, and 64-bit longs (on Linux) are shrunk into 32-bit longs wherever it is legal and safe to do so. In order for this option to be effective the compiler must be able to optimize using the -ipo/-Qipo option and must be able to analyze all library/external calls the program makes.

    This option requires that the size of the program executable never exceeds 2**32 bytes and all data values can be represented within 32 bits. If the program can run correctly in a 32-bit system, these requirements are implicitly satisfied. If the program violates these size restrictions, unpredictable behavior might occur.

• • -Qipo
  • 
  • OPTIMIZE

  • Multi-file ip optimizations that includes:
    - inline function expansion
    - interprocedural constant propogation
    - dead code elimination
    - propagation of function characteristics
    - passing arguments in registers
    - loop-invariant code motion

• • -O3
  • 
  • OPTIMIZE

  • Enables O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enables optimizations for maximum speed, such as:

    • Loop unrolling, including instruction scheduling
    • Code replication to eliminate branches
    • Padding the size of certain power-of-two arrays to allow more efficient cache use.

    On Windows systems, the O3 option sets the /GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2 option.

    On Linux and Mac OS X systems, the O3 option sets option -fomit-frame-pointer.

    On systems using IA-32 architecture or Intel64 architecture, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times.

    On systems using IA-64 architecture, the O3 option enables optimizations for technical computing applications (loop-intensive code): loop\ optimizations and data prefetch.

    The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations.
    The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.

  • Includes:
    • -GF
    • -Gf
    • -Ob_n
    • -O2
      • -Oi-
      • -Gs
      • -Oy
      • -Gy
      • -Os
      • -GF
      • -Gf
      • -Ob_n
      • -Og
      • -O1
        • -Qunroll_n
        • -Oi-
        • -Op-
        • -Oy
        • -Gy
        • -Os
        • -GF
        • -Gf
        • -Ob_n
        • -Og
• • -Qprec-div-
  • 
  • OPTIMIZE

  • This option improves precision of floating-point divides. It has a slight impact on speed.

    With some optimizations, such as -xSSE2 (Linux) or /QxSSE2 (Windows), the compiler may change floating-point division computations into multiplication by the reciprocal of the denominator. For example, A/B is computed as A * (1/B) to improve the speed of the computation.

    However, sometimes the value produced by this transformation is not as accurate as full IEEE division. When it is important to have fully precise IEEE division, use this option to disable the floating-point division-to-multiplication optimization. The result is more accurate, with some loss of performance.

    If you specify -no-prec-div (Linux and Mac OS X) or /Qprec-div- (Windows), it enables optimizations that give slightly less precise results than full IEEE division.

    Default: -prec-div or/Qprec-div

• • -Qparallel
  • 
  • Yes
  • OPTIMIZE

  • This option tells the auto-parallelizer to generate multithreaded code for loops that can be safely executed in parallel.
    To use this option, you must also specify option O2 or O3.

• • -Qopt-prefetch
  • 
  • OPTIMIZE

  • This option enables or disables prefetch insertion optimization. The goal of prefetching is to reduce cache misses by providing hints to the processor about when data should be loaded into the cache.

    On IA-32 architecture and Intel 64 architecture, this option enables prefetching when higher optimization levels are specified.

• • /F1000000000
  • 
  • EXTRA_LDFLAGS

  • set the stack reserve amount specified to the linker.

Benchmarks using both Fortran and C

• • -QxSSE4.2
  • 
  • OPTIMIZE

  • Tells the compiler to generate optimized code specialized for the Intel processor that executes your program.
    Syntax -Qx(processor)

    (processor)indicates the processor for which code is generated. Many of the following descriptions refer to Intel® Streaming SIMD Extensions

    Host
    Can generate instructions for the highest instruction set available on the compilation host processor.
    On Intel processors, this may correspond to the most suitable –x (Linux* and Mac OS* X) or /Qx (Windows*) option. On non-Intel processors, this may correspond to the most suitable –m (Linux and Mac OS X) or /arch (Windows) option. The resulting executable may not run on a processor different from the host in the following cases:
    If the processor does not support all of the instructions supported by the host processor.
    If the host is an Intel processor and the other processor is a non-Intel processor.

    AVX
    Optimizes for Intel processors that support Intel® Advanced Vector Extensions (Intel® AVX).

    SSE4.2
    Can generate Intel® SSE4 Efficient Accelerated String and Text Processing instructions supported by Intel® Core™ i7 processors. Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator, Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for the Intel® Core™ processor family.

    SSE4.1
    Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator instructions for Intel processors. Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for Intel® 45nm Hi-k next generation Intel® Core™ microarchitecture. This replaces value S, which is deprecated.

    SSE3_ATOM
    Optimizes for the Intel® Atom™ processor and Intel® Centrino® Atom™ Processor Technology. Can generate MOVBE instructions, depending on the setting of option -minstruction (Linux and Mac OS) or /Qinstruction (Windows).

    SSSE3
    Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for the Intel® Core™2 Duo processor family. For Mac OS* X systems, this value is only supported on Intel® 64 architecture. This replaces value T, which is deprecated.

    SSE3
    Can generate Intel® SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for processors based on Intel® Core™ microarchitecture and Intel NetBurst® microarchitecture. For Mac OS* X systems, this value is only supported on IA-32 architecture.This replaces value P, which is deprecated.

    SSE2
    Can generate Intel® SSE2 and SSE instructions for Intel processors, and it can optimize for Intel® Pentium® 4 processors, Intel® Pentium® M processors, and Intel® Xeon® processors with Intel® SSE2. This value is not available on Mac OS* X systems. This replaces value N, which is deprecated.

    Default
    Windows systems: None
    Linux systems: None
    Mac OS X systems using IA-32 architecture: SSE3
    Mac OS X systems using Intel® 64 architecture: SSSE3
    On Windows systems, if neither /Qx nor /arch is specified, the default is /arch:SSE2.
    On Linux systems, if neither -x nor -m is specified, the default is -msse2.

    Description
    This option tells the compiler to generate optimized code specialized for the Intel processor that executes your program. It also enables optimizations in addition to Intel processor-specific optimizations. The specialized code generated by this option may run only on a subset of Intel processors.

    This option can enable optimizations depending on the argument specified. For example, it may enable Intel® Streaming SIMD Extensions 4 (Intel® SSE4), Intel® Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3), Intel® Streaming SIMD Extensions 3 (Intel® SSE3), Intel® Streaming SIMD Extensions 2 (Intel® SSE2), or Intel® Streaming SIMD Extensions (Intel® SSE) instructions.

    The binaries produced by these values will run on Intel processors that support all of the features for the targeted processor. For example, binaries produced with SSE3 will run on an Intel® Core™ 2 Duo processor, because that processor completely supports all of the capabilities of the Intel® Pentium® 4 processor, which the SSE3 value targets. Specifying the SSSE3 value has the potential of using more features and optimizations available to the Intel® Core™ 2 Duo processor.

    Do not use processor values to create binaries that will execute on a processor that is not compatible with the targeted processor. The resulting program may fail with an illegal instruction exception or display other unexpected behavior. For example, binaries produced with SSE3 may produce code that will not run on Intel® Pentium® III processors or earlier processors that do not support SSE3 instructions.

    Compiling the function main() with any of the processor values produces binaries that display a fatal run-time error if they are executed on unsupported processors. For more information, see Optimizing Applications.

    If you specify more than one processor value, code is generated for only the highest-performing processor specified. The highest-performing to lowest-performing processor values are: SSE4.2, SSE4.1, SSSE3, SSE3, SSE2.Note that processor values AVX and SSE3_ATOM do not fit within this group.

    Compiler options m and arch produce binaries that should run on processors not made by Intel that implement the same capabilities as the corresponding Intel processors.

    Previous value O is deprecated and has been replaced by option -msse3 (Linux and Mac OS X) and option /arch:SSE3 (Windows).

    Previous values W and K are deprecated. The details on replacements are as follows:

    • Mac OS X systems: On these systems, there is no exact replacement for W or K. You can upgrade to the default option -msse3 (IA-32 architecture) or option -mssse3 (Intel® 64 architecture).
    • Windows and Linux systems: The replacement for W is -msse2 (Linux) or /arch:SSE2 (Windows).

    There is no exact replacement for K. However, on Windows systems, /QxK is interpreted as /arch:IA32; on Linux systems, -xK is interpreted as -mia32. You can also do one of the following:

    • Upgrade to option -msse2 (Linux) or option /arch:SSE2 (Windows). This will produce one code path that is specialized for Intel® SSE2. It will not run on earlier processors.
    • Specify the two option combination -mia32 -axSSE2 (Linux) or /arch:IA32 /QaxSSE2 (Windows). This combination will produce an executable that runs on any processor with IA-32 architecture but with an additional specialized Intel® SSE2 code path.

    The -x and /Qx options enable additional optimizations not enabled with option -m or option /arch.

    On Windows* systems, options /Qx and /arch are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning. Similarly, on Linux* and Mac OS* X systems, options -x and -m are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning.

• • -Qauto-ilp32
  • 
  • OPTIMIZE

  • This option instructs the compiler to analyze and transform the program so that 64-bit pointers are shrunk to 32-bit pointers, and 64-bit longs (on Linux) are shrunk into 32-bit longs wherever it is legal and safe to do so. In order for this option to be effective the compiler must be able to optimize using the -ipo/-Qipo option and must be able to analyze all library/external calls the program makes.

    This option requires that the size of the program executable never exceeds 2**32 bytes and all data values can be represented within 32 bits. If the program can run correctly in a 32-bit system, these requirements are implicitly satisfied. If the program violates these size restrictions, unpredictable behavior might occur.

• • -Qipo
  • 
  • OPTIMIZE

  • Multi-file ip optimizations that includes:
    - inline function expansion
    - interprocedural constant propogation
    - dead code elimination
    - propagation of function characteristics
    - passing arguments in registers
    - loop-invariant code motion

• • -O3
  • 
  • OPTIMIZE

  • Enables O2 optimizations plus more aggressive optimizations, such as prefetching, scalar replacement, and loop and memory access transformations. Enables optimizations for maximum speed, such as:

    • Loop unrolling, including instruction scheduling
    • Code replication to eliminate branches
    • Padding the size of certain power-of-two arrays to allow more efficient cache use.

    On Windows systems, the O3 option sets the /GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2 option.

    On Linux and Mac OS X systems, the O3 option sets option -fomit-frame-pointer.

    On systems using IA-32 architecture or Intel64 architecture, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times.

    On systems using IA-64 architecture, the O3 option enables optimizations for technical computing applications (loop-intensive code): loop\ optimizations and data prefetch.

    The O3 optimizations may not cause higher performance unless loop and memory access transformations take place. The optimizations may slow down code in some cases compared to O2 optimizations.
    The O3 option is recommended for applications that have loops that heavily use floating-point calculations and process large data sets.

  • Includes:
    • -GF
    • -Gf
    • -Ob_n
    • -O2
      • -Oi-
      • -Gs
      • -Oy
      • -Gy
      • -Os
      • -GF
      • -Gf
      • -Ob_n
      • -Og
      • -O1
        • -Qunroll_n
        • -Oi-
        • -Op-
        • -Oy
        • -Gy
        • -Os
        • -GF
        • -Gf
        • -Ob_n
        • -Og
• • -Qprec-div-
  • 
  • OPTIMIZE

  • This option improves precision of floating-point divides. It has a slight impact on speed.

    With some optimizations, such as -xSSE2 (Linux) or /QxSSE2 (Windows), the compiler may change floating-point division computations into multiplication by the reciprocal of the denominator. For example, A/B is computed as A * (1/B) to improve the speed of the computation.

    However, sometimes the value produced by this transformation is not as accurate as full IEEE division. When it is important to have fully precise IEEE division, use this option to disable the floating-point division-to-multiplication optimization. The result is more accurate, with some loss of performance.

    If you specify -no-prec-div (Linux and Mac OS X) or /Qprec-div- (Windows), it enables optimizations that give slightly less precise results than full IEEE division.

    Default: -prec-div or/Qprec-div

• • -Qparallel
  • 
  • Yes
  • OPTIMIZE

  • This option tells the auto-parallelizer to generate multithreaded code for loops that can be safely executed in parallel.
    To use this option, you must also specify option O2 or O3.

• • -Qopt-prefetch
  • 
  • OPTIMIZE

  • This option enables or disables prefetch insertion optimization. The goal of prefetching is to reduce cache misses by providing hints to the processor about when data should be loaded into the cache.

    On IA-32 architecture and Intel 64 architecture, this option enables prefetching when higher optimization levels are specified.

• • /F1000000000
  • 
  • EXTRA_LDFLAGS

  • set the stack reserve amount specified to the linker.