SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2005 Standard Performance Evaluation Corporation
IBM Corporation
IBM System p5 520 (1650 MHz, 2 CPU)
SPECint_rate2000 = 34.8  
SPECint_rate_base2000 = 34.4  
SPEC license # 11 Tested by: IBM Test date: Dec-2005 Hardware Avail: Feb-2006 Software Avail: Feb-2006
Graph Scale Benchmark Base
Copies
Base
Runtime
Base
Ratio
Copies Runtime Ratio
164.gzip base result bar (23.3)
164.gzip peak result bar (23.5)
164.gzip 4 278    23.3   4 276    23.5  
175.vpr base result bar (29.4)
175.vpr peak result bar (29.6)
175.vpr 4 221    29.4   4 219    29.6  
176.gcc base result bar (36.7)
176.gcc peak result bar (37.4)
176.gcc 4 139    36.7   4 136    37.4  
181.mcf base result bar (48.9)
181.mcf peak result bar (42.4)
181.mcf 4 171    48.9   4 197    42.4  
186.crafty base result bar (26.9)
186.crafty peak result bar (32.1)
186.crafty 4 172    26.9   4 145    32.1  
197.parser base result bar (33.4)
197.parser peak result bar (33.1)
197.parser 4 250    33.4   4 252    33.1  
252.eon base result bar (40.5)
252.eon peak result bar (40.6)
252.eon 4 149    40.5   4 149    40.6  
253.perlbmk base result bar (26.5)
253.perlbmk peak result bar (28.2)
253.perlbmk 4 315    26.5   4 297    28.2  
254.gap base result bar (33.5)
254.gap peak result bar (33.7)
254.gap 4 152    33.5   4 151    33.7  
255.vortex base result bar (55.7)
255.vortex peak result bar (58.5)
255.vortex 4 158    55.7   4 151    58.5  
256.bzip2 base result bar (36.8)
256.bzip2 peak result bar (38.0)
256.bzip2 4 189    36.8   4 183    38.0  
300.twolf base result bar (33.3)
300.twolf peak result bar (31.9)
300.twolf 4 418    33.3   4 436    31.9  
  SPECint_rate_base2000 34.4    
  SPECint_rate2000 34.8  

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM System p5 520 (1650 MHz, 2 CPU)
CPU: POWER5+
CPU MHz: 1650
FPU: Integrated
CPU(s) enabled: 2 cores, 1 chip, 2 cores/chip (SMT on)
CPU(s) orderable: 1,2
Parallel: No
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified, shared (on chip)/chip
L3 Cache: 36MB unified (off-chip)/DCM, 1 DCM/SUT
Other Cache: None
Memory: 8x2GB
Disk Subsystem: 2x73GB SCSI, 15K RPM
Other Hardware: None
Software
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 8.0 for AIX
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information
  Portability Flags:
    176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
    186.crafty:   -DAIX
    253.perlbmk:  -DSPEC_CPU2000_AIX
    254.gap:      -DSYS_IS_BSD -DSYS_STRING_H
                  -DSYS_HAS_MALLOC_PROTO -DSYS_HAS_CALLOC_PROTO
    300.twolf:    -DHAVE_SIGNED_CHAR
 
  Base Optimization Flags:
    C:    -qpdf1/pdf2
          -O5 -blpdata -D_ILS_MACROS
    C++:  -qpdf1/pdf2
          -O4 -qalign=natural
 
  Peak Optimization Flags
    164.gzip:     -qpdf1/pdf2
                  -O4 -qfdpr -blpdata
                  fdpr -q -O3
    175.vpr:      -qpdf1/pdf2
                  -O5 -qfdpr -blpdata
                  fdpr -q -O3
    176.gcc:      -qpdf1/pdf2
                  -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -blpdata
    181.mcf:      -qpdf1/pdf2
                  -O4 -qalign=natural -blpdata
    186.crafty:   -qpdf1/pdf2
                  -O4 -qalign=natural -q64 -lhmu -blpdata
    197.parser:   -qpdf1/pdf2
                  -O4 -qfdpr -D_ILS_MACROS -blpdata
                  fdpr -q -O3
    252.eon:      -qpdf1/pdf2
                  -O4 -qalign=natural
    253.perlbmk:  -qpdf1/pdf2
                  -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -blpdata -lhmu
    254.gap:      -qpdf1/pdf2
                  -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -blpdata
    255.vortex:   -qpdf1/pdf2
                  -O4 -qfdpr -lhmu -blpdata
                  fdpr -q -O3
    256.bzip2:    -qpdf1/pdf2
                  -O5 -qfdpr -blpdata
                  fdpr -q -O3
    300.twolf:    -O5 -qfdpr -blpdata
                  fdpr -q -O3
 
 
  The installed OS level is AIX 5L for POWER version 5.3 with the 5300-04 Recommended Technology Level.
 
  SMT:  Acronym for "Simultaneous Multi-Threading". A processor technology that allows
        the simultaneous execution of multiple thread contexts within a single processor
        core. (Enabled by default)
  DCM:  Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
  SUT:  Acronym for "System Under Test"
 
  Extended C:     IBM XL C for AIX invoked as cc
  C++:            IBM XL C for AIX invoked as xlC
 
  ulimits set to unlimited.
  Large page mode and memory affinity were set as follows:
      vmo -r -o lgpg_regions=400 -o lgpg_size=16777216
      chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
      shutdown -rF
      export MEMORY_AFFINITY=MCM
 
  The following config-file entry was used to assign each benchmark process to a core:
       submit = bindprocessor \$\$ \$SPECUSERNUM; $command
  The "bindprocessor" AIX command binds a process to a CPU core.
 


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Copyright © 1999-2005 Standard Performance Evaluation Corporation

First published at SPEC.org on 08-Mar-2006

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