SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2005 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer Bladecenter HS20 (3.8 GHz Xeon, 2MB L2 Cache)
SPECint2000 = 1812     
SPECint_base2000 = 1802     
SPEC license # 11 Tested by: IBM Corporation Test date: Sep-2005 Hardware Avail: Sep-2005 Software Avail: Jun-2005
Benchmark Reference
Time		 Base
Runtime		 Base
Ratio		 Runtime Ratio Graph Scale
164.gzip 1400 113    1237      112    1249      164.gzip base result bar (1237)
164.gzip peak result bar (1249)
175.vpr 1400 115    1219      112    1254      175.vpr base result bar (1219)
175.vpr peak result bar (1254)
176.gcc 1100 51.2  2148      51.2  2148      176.gcc base result bar (2148)
176.gcc peak result bar (2148)
181.mcf 1800 91.2  1974      91.2  1974      181.mcf base result bar (1974)
181.mcf peak result bar (1974)
186.crafty 1000 71.2  1405      71.4  1400      186.crafty base result bar (1405)
186.crafty peak result bar (1400)
197.parser 1800 117    1541      116    1547      197.parser base result bar (1541)
197.parser peak result bar (1547)
252.eon 1300 54.7  2379      54.8  2372      252.eon base result bar (2379)
252.eon peak result bar (2372)
253.perlbmk 1800 81.7  2203      81.8  2201      253.perlbmk base result bar (2203)
253.perlbmk peak result bar (2201)
254.gap 1100 55.8  1970      54.5  2019      254.gap base result bar (1970)
254.gap peak result bar (2019)
255.vortex 1900 60.8  3123      60.7  3129      255.vortex base result bar (3123)
255.vortex peak result bar (3129)
256.bzip2 1500 110    1363      110    1365      256.bzip2 base result bar (1363)
256.bzip2 peak result bar (1365)
300.twolf 3000 155    1933      155    1933      300.twolf base result bar (1933)
300.twolf peak result bar (1933)
SPECint_base2000 1802       
  SPECint2000 1812       

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM eServer Bladecenter HS20 (3.8 GHz Xeon, 2MB L2 Cache)
CPU: Intel Xeon 3.8 (800 MHz system bus)
CPU MHz: 3800
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 1 core/chip (Hyper-Threading Technology disabled)
CPU(s) orderable: 1,2
Parallel: No
Primary Cache: 12K(I) micro-ops + 16KB(D) on chip
Secondary Cache: 2048KB(I+D) on chip
L3 Cache: N/A
Other Cache: N/A
Memory: 4 x 2048 MB ECC PC2-3200 Dual Rank
Disk Subsystem: 36GB SCSI 10K RPM
Other Hardware:
Software
Operating System: Windows Server 2003 Standard Edition
Compiler: Intel C/C++ Compiler 9.0 (20050624Z) for 32-bit applications
Intel Fortran Compiler 9.0 (20050624Z) for 32-bit applications
Microsoft Visual Studio .NET 13.0.9466 (for libraries)
MicroQuill Smartheap Library 7.30
File System: NTFS
System State: Default
Notes / Tuning Information 
 GENERAL
   ONESTEP=yes
   +FDO:   PASS1=-Qprof_gen  PASS2=-Qprof_use
 PORTABILITY FLAGS
   176.gcc:     -Dalloca=_alloca /F10000000
   186.crafty:  -DNT_i386
   252.eon:	   srcalt=stdcpp
   253.perlbmk: -DSPEC_CPU2000_NTOS -DPERLDLL /MT
   254.gap:     -DSYS_HAS_CALLOC_PROTO -DSYS_HAS_MALLOC_PROTO
 BASE TUNING
   C:           -fast -Qansi_alias +FDO shlW32M.lib
   C++:         -fast -Qcxx_features +FDO
 PEAK TUNING
   164.gzip:    -fast +FDO
   175.vpr:     -fast +FDO
   176.gcc:     basepeak=yes
   181.mcf:     -fast +FDO shlW32M.lib
   186.crafty:  -fast -Oa +FDO shlW32M.lib
   197.parser:  -fast +FDO 
   252.eon:     -fast +FDO
   253.perlbmk: -fast -Oa +FDO shlW32M.lib
   254.gap:     -fast +FDO
   255.vortex   -fast +FDO shlw32M.lib
   256.bzip2:   -fast -Qunroll1 -Oa +FDO shlw32M.lib
   300.twolf:   -fast +FDO shlW32M.lib
 EXTRA LIBRARIES
   shlW32M.lib: MicroQuill SmartHeap Library 7.1
                www.microquill.com

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Copyright © 1999-2005 Standard Performance Evaluation Corporation

First published at SPEC.org on 04-Oct-2005

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