SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer i5 550 (1650 MHz, 1 CPU)
SPECint2000 = 1248     
SPECint_base2000 = 1200     
SPEC license # 11 Tested by: IBM Test date: Jun-2004 Hardware Avail: Aug-2004 Software Avail: Aug-2004
Benchmark Reference
Time		 Base
Runtime		 Base
Ratio		 Runtime Ratio Graph Scale
164.gzip 1400 194    722     189    742     164.gzip base result bar (722)
164.gzip peak result bar (742)
175.vpr 1400 132    1063      132    1063      175.vpr base result bar (1063)
175.vpr peak result bar (1063)
176.gcc 1100 82.7  1330      82.7  1330      176.gcc base result bar (1330)
176.gcc peak result bar (1330)
181.mcf 1800 83.0  2169      79.1  2274      181.mcf base result bar (2169)
181.mcf peak result bar (2274)
186.crafty 1000 98.6  1014      79.4  1260      186.crafty base result bar (1014)
186.crafty peak result bar (1260)
197.parser 1800 167    1075      166    1083      197.parser base result bar (1075)
197.parser peak result bar (1083)
252.eon 1300 94.2  1380      94.2  1380      252.eon base result bar (1380)
252.eon peak result bar (1380)
253.perlbmk 1800 211    851     194    928     253.perlbmk base result bar (851)
253.perlbmk peak result bar (928)
254.gap 1100 103    1065      103    1065      254.gap base result bar (1065)
254.gap peak result bar (1065)
255.vortex 1900 100    1896      94.4  2014      255.vortex base result bar (1896)
255.vortex peak result bar (2014)
256.bzip2 1500 130    1153      130    1153      256.bzip2 base result bar (1153)
256.bzip2 peak result bar (1153)
300.twolf 3000 222    1354      217    1381      300.twolf base result bar (1354)
300.twolf peak result bar (1381)
SPECint_base2000 1200       
  SPECint2000 1248       

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM eServer i5 550 (1650 MHz, 1 CPU)
CPU: POWER5
CPU MHz: 1650
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 2 cores/chip (SMT off)
CPU(s) orderable: 2,4
Parallel: No
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified (on chip)/chip
L3 Cache: 36MB unified (off chip)/DCM, 2 DCM/SUT
Other Cache: none
Memory: 16x4 GB
Disk Subsystem: 1x36GB SCSI, 15K RPM
Other Hardware:
Software
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 7.0 for AIX
File System: AIX/JFS2
System State: Multi-User
Notes / Tuning Information 
 Portability Flags:
   176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
   186.crafty:   -DAIX
   252.eon:      srcalt=fmax_errno 
                 -I. -DNDEBUG
   253.perlbmk:  -DSPEC_CPU2000_AIX
   254.gap:      -DSYS_IS_BSD -DSYS_STRING_H -DSYS_HAS_TIME_PROTO
                 -DSYS_HAS_MALLOC_PROTO -DSYS_HAS_CALLOC_PROTO
   300.twolf:    -DHAVE_SIGNED_CHAR
 
 
 Base Optimization Flags:
   C:    -qpdf1/pdf2 
         -O5 -blpdata -D_ILS_MACROS
   C++:  -qpdf1/pdf2 
         -O5 -lhmu -qalign=natural
 
 
 Peak Optimization Flags
   164.gzip:     -qpdf1/pdf2
                 -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -D_ILS_MACROS
                 "CC=xlc"
   175.vpr:      basepeak = 1 
   176.gcc:      basepeak = 1
   181.mcf:      fdpr -quiet -R3
                 -O5 -blpdata -qfdpr -D_ILS_MACROS
   186.crafty:   -qpdf1/pdf2
                 fdpr -quiet -R3
                 -O4 -q64 -qfdpr -qarch=pwr3 -qtune=pwr3 -D_ILS_MACROS
   197.parser:   -qpdf1/pdf2
                 fdpr -quiet -R3
                 -O5 -blpdata -D_ILS_MACROS -qfdpr
   252.eon:      basepeak = 1
   253.perlbmk:  -qpdf1/pdf2
                 -O5 -D_ILS_MACROS -lhmu -qalign=natural
   254.gap:      basepeak = 1
   255.vortex:   -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural -D_ILS_MACROS -blpdata
   256.bzip2:    basepeak = 1
   300.twolf:    -O5 -lhmu -blpdata -qalign=natural
                 "CC = xlc"

 Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
 was used with 252.eon for POSIX-compatibility.

 SMT: Acronym for "Simultaneous Multi-Threading". A processor technology that allows
      the simultaneous execution of multiple thread contexts within a single processor
      core. (Enabled by default)
 DCM: Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
 SUT: Acronym for "System Under Test"

 ulimits set to unlimited.
 Large page mode and memory affinity were set as follows:
    vmo -r -o lgpg_regions=400 -o lgpg_size=16777216 -o memory_affinity=1
    chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
    reboot -q
    export MEMORY_AFFINITY=MCM
 Three cores were deconfigured and SMT disabled at the open-firmware prompt, using the
 command
    boot -s cpu=1 -s smt_off
 This result was measured on model IBM eServer p5 550.
 Model i5 550 and model p5 550 are electronically equivalent.

For questions about this result, please contact the tester.
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Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 07-Sep-2004

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