SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer p5 570 (1900 MHz, 8 CPU)
SPECint_rate2000 = 147    
SPECint_rate_base2000 = 141    
SPEC license # 11 Tested by: IBM Test date: Jun-2004 Hardware Avail: Sep-2004 Software Avail: Aug-2004
Graph Scale Benchmark Base
Copies		 Base
Runtime		 Base
Ratio		 Copies Runtime Ratio
164.gzip base result bar (110)
164.gzip peak result bar (110)		 164.gzip 16 236    110     16 235    110    
175.vpr base result bar (123)
175.vpr peak result bar (123)		 175.vpr 16 211    123     16 211    123    
176.gcc base result bar (162)
176.gcc peak result bar (162)		 176.gcc 16 126    162     16 126    162    
181.mcf base result bar (190)
181.mcf peak result bar (132)		 181.mcf 16 176    190     16 254    132    
186.crafty base result bar (110)
186.crafty peak result bar (150)		 186.crafty 16 169    110     16 124    150    
197.parser base result bar (88.4)
197.parser peak result bar (135)		 197.parser 16 378    88.4   16 247    135    
252.eon base result bar (176)
252.eon peak result bar (176)		 252.eon 16 137    176     16 137    176    
253.perlbmk base result bar (113)
253.perlbmk peak result bar (123)		 253.perlbmk 16 296    113     16 271    123    
254.gap base result bar (142)
254.gap peak result bar (146)		 254.gap 16 144    142     16 139    146    
255.vortex base result bar (233)
255.vortex peak result bar (245)		 255.vortex 16 151    233     16 144    245    
256.bzip2 base result bar (160)
256.bzip2 peak result bar (162)		 256.bzip2 16 174    160     16 172    162    
300.twolf base result bar (141)
300.twolf peak result bar (140)		 300.twolf 16 395    141     16 399    140    
  SPECint_rate_base2000 141      
  SPECint_rate2000 147    

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM eServer p5 570 (1900 MHz, 8 CPU)
CPU: POWER5
CPU MHz: 1900
FPU: Integrated
CPU(s) enabled: 8 cores, 4 chips, 2 cores/chip (SMT on)
CPU(s) orderable: 2,4,8,12,16
Parallel: No
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified (on chip)/chip
L3 Cache: 36MB unified (off chip)/DCM, 4 DCM/SUT
Other Cache: none
Memory: 32x1 GB DDR2
Disk Subsystem: 1x36GB SCSI, 15K RPM
Other Hardware:
Software
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 7.0 for AIX
File System: AIX/JFS2
System State: Multi-User
Notes / Tuning Information 
 Portability Flags:
   176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
   186.crafty:   -DAIX
   252.eon:      srcalt=fmax_errno 
                 -I. -DNDEBUG
   253.perlbmk:  -DSPEC_CPU2000_AIX
   254.gap:      -DSYS_IS_BSD -DSYS_STRING_H -DSYS_HAS_TIME_PROTO
                 -DSYS_HAS_MALLOC_PROTO -DSYS_HAS_CALLOC_PROTO
   300.twolf:    -DHAVE_SIGNED_CHAR
 
 
 Base Optimization Flags:
   C:    -qpdf1/pdf2 
         -O5 -blpdata -qalign=natural
   C++:  -qpdf1/pdf2 
         -O5 -lhmu -qalign=natural
 
 
 Peak Optimization Flags
   164.gzip:     -qpdf1/pdf2
                 -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -D_ILS_MACROS
                 "CC=xlc"
   175.vpr:      basepeak = 1 
   176.gcc:      basepeak = 1
   181.mcf:      fdpr -quiet -R3
                 -O5 -blpdata -qfdpr
   186.crafty:   -qpdf1/pdf2
                 fdpr -quiet -R3
                 -O4 -q64 -qfdpr -qarch=pwr3 -qtune=pwr3 -D_ILS_MACROS
   197.parser:   -qpdf1/pdf2
                 fdpr -quiet -R3
                 -O4 -blpdata -D_ILS_MACROS -qfdpr -qarch=pwr3 -qtune=pwr3
   252.eon:      basepeak = 1
   253.perlbmk:  -qpdf1/pdf2
                 -O5 -D_ILS_MACROS -lhmu -qalign=natural
   254.gap:      -qpdf1/pdf2
                 -O4 -qarch=pwr4 -qtune=pwr4 -D_ILS_MACROS -lhmu -qalign=natural
   255.vortex:   -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural -D_ILS_MACROS -blpdata
   256.bzip2:    -qpdf1/pdf2
                 -O5 -blpdata -qarch=pwr3 -qtune=pwr3 -qalign=natural
   300.twolf:    -O5 -lhmu -blpdata -qalign=natural
                 "CC = xlc"

 Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
 was used with 252.eon for POSIX-compatibility.

 SMT: Acronym for "Simultaneous Multi-Threading". A processor technology that allows
      the simultaneous execution of multiple thread contexts within a single processor
      core. (Enabled by default)
 DCM: Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
 SUT: Acronym for "System Under Test"

 ulimits set to unlimited.
 Large page mode and memory affinity were set as follows:
    vmo -r -o lgpg_regions=800 -o lgpg_size=16777216 -o memory_affinity=1
    chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
    reboot -q
    export MEMORY_AFFINITY=MCM

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Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 28-Jul-2004

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